| Message ID | 20230228022150.1657843-7-alan.previn.teres.alexis@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915/pxp: Add MTL PXP Support | expand |
On 2/27/2023 6:21 PM, Alan Previn wrote: > Despite KCR subsystem being in the media-tile (close to the > GSC-CS), the IRQ controls for it are on GT-0 with other global > IRQ controls. Thus, add a helper for KCR hw interrupt > enable/disable functions to get the correct gt structure (for > uncore) for MTL. This is not correct. On MTL, the interrupts logic isn't on any particular GT, it is in a shared area. The fact that we handle all interrupts as if they were triggered on the root GT is an i915 implementation decision. Both uncores have access to the irq regs and the 2 GTs share the irq lock. A comparable example is the media GuC, where the interrupts enable/disable functions are called with the media GT structure. > In the helper, we get GT-0's handle for uncore when touching > IRQ registers despite the pxp->ctrl_gt being the media-tile. > No difference for legacy of course. > > Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com> > --- > drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c | 2 +- > drivers/gpu/drm/i915/pxp/intel_pxp_irq.c | 24 +++++++++++++++++--- > drivers/gpu/drm/i915/pxp/intel_pxp_irq.h | 8 +++++++ > 3 files changed, 30 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c b/drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c > index 4b8e70caa3ad..9f6e300486b4 100644 > --- a/drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c > +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c > @@ -44,7 +44,7 @@ static int pxp_terminate_get(void *data, u64 *val) > static int pxp_terminate_set(void *data, u64 val) > { > struct intel_pxp *pxp = data; > - struct intel_gt *gt = pxp->ctrl_gt; > + struct intel_gt *gt = intel_pxp_get_irq_gt(pxp); In this function the only use you have of the GT is to take gt->irq_lock, but that's shared between the GTs so it is ok to use the media GT for it. > > if (!intel_pxp_is_active(pxp)) > return -ENODEV; > diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c b/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c > index 91e9622c07d0..3a725397349f 100644 > --- a/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c > +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c > @@ -4,10 +4,12 @@ > */ > #include <linux/workqueue.h> > > +#include "gt/intel_gt.h" > #include "gt/intel_gt_irq.h" > #include "gt/intel_gt_regs.h" > #include "gt/intel_gt_types.h" > > +#include "i915_drv.h" > #include "i915_irq.h" > #include "i915_reg.h" > > @@ -17,6 +19,22 @@ > #include "intel_pxp_types.h" > #include "intel_runtime_pm.h" > > +/** > + * intel_pxp_get_irq_gt - Find the correct GT that owns KCR interrupts > + * @pxp: pointer to pxp struct > + * > + * For platforms with a single GT, we return the pxp->ctrl_gt (as expected) > + * but for MTL+ that has a media-tile, although the KCR engine is in the > + * media-tile (i.e. pxp->ctrl_gt), the IRQ controls are on the root tile. > + * In the end, we don't use pxp->ctrl_gt for IRQ, we always return root gt. > + */ > +struct intel_gt *intel_pxp_get_irq_gt(struct intel_pxp *pxp) > +{ > + WARN_ON_ONCE(!pxp->ctrl_gt->i915->media_gt && !gt_is_root(pxp->ctrl_gt)); > + > + return to_gt(pxp->ctrl_gt->i915); > +} > + > /** > * intel_pxp_irq_handler - Handles PXP interrupts. > * @pxp: pointer to pxp struct > @@ -29,7 +47,7 @@ void intel_pxp_irq_handler(struct intel_pxp *pxp, u16 iir) > if (GEM_WARN_ON(!intel_pxp_is_enabled(pxp))) > return; > > - gt = pxp->ctrl_gt; > + gt = intel_pxp_get_irq_gt(pxp); same as above, only use here is the lock. > > lockdep_assert_held(gt->irq_lock); > > @@ -68,7 +86,7 @@ static inline void pxp_irq_reset(struct intel_gt *gt) > > void intel_pxp_irq_enable(struct intel_pxp *pxp) > { > - struct intel_gt *gt = pxp->ctrl_gt; > + struct intel_gt *gt = intel_pxp_get_irq_gt(pxp); in this function we use the gt for: 1 - the lock: see above about this 2 - gen11_gt_reset_one_iir(): this should work with the media GT (we use it for media GuC) 3 - writes to the GEN11_CRYPTO_* regs: those should also work with the media GT uncore as these regs are in the same range as the GuC scratch regs and we use the media uncore for those accesses. > > spin_lock_irq(gt->irq_lock); > > @@ -83,7 +101,7 @@ void intel_pxp_irq_enable(struct intel_pxp *pxp) > > void intel_pxp_irq_disable(struct intel_pxp *pxp) > { > - struct intel_gt *gt = pxp->ctrl_gt; > + struct intel_gt *gt = intel_pxp_get_irq_gt(pxp); > AFAICS this functions uses the same 3 cases as above. Overall, I am not sure this patch is required. Am I missing something? Daniele > /* > * We always need to submit a global termination when we re-enable the > diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_irq.h b/drivers/gpu/drm/i915/pxp/intel_pxp_irq.h > index 8c292dc86f68..eea87c9eb62b 100644 > --- a/drivers/gpu/drm/i915/pxp/intel_pxp_irq.h > +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_irq.h > @@ -9,6 +9,7 @@ > #include <linux/types.h> > > struct intel_pxp; > +struct intel_gt; > > #define GEN12_DISPLAY_PXP_STATE_TERMINATED_INTERRUPT BIT(1) > #define GEN12_DISPLAY_APP_TERMINATED_PER_FW_REQ_INTERRUPT BIT(2) > @@ -23,6 +24,8 @@ struct intel_pxp; > void intel_pxp_irq_enable(struct intel_pxp *pxp); > void intel_pxp_irq_disable(struct intel_pxp *pxp); > void intel_pxp_irq_handler(struct intel_pxp *pxp, u16 iir); > +struct intel_gt *intel_pxp_get_irq_gt(struct intel_pxp *pxp); > + > #else > static inline void intel_pxp_irq_handler(struct intel_pxp *pxp, u16 iir) > { > @@ -35,6 +38,11 @@ static inline void intel_pxp_irq_enable(struct intel_pxp *pxp) > static inline void intel_pxp_irq_disable(struct intel_pxp *pxp) > { > } > + > +static inline struct intel_gt *intel_pxp_get_irq_gt(struct intel_pxp *pxp) > +{ > + return NULL; > +} > #endif > > #endif /* __INTEL_PXP_IRQ_H__ */
> alan:snip > > void intel_pxp_irq_enable(struct intel_pxp *pxp) > > { > > - struct intel_gt *gt = pxp->ctrl_gt; > > + struct intel_gt *gt = intel_pxp_get_irq_gt(pxp); > > in this function we use the gt for: > > 1 - the lock: see above about this > > 2 - gen11_gt_reset_one_iir(): this should work with the media GT (we use > it for media GuC) > > 3 - writes to the GEN11_CRYPTO_* regs: those should also work with the > media GT uncore as these regs are in the same range as the GuC scratch > regs and we use the media uncore for those accesses. > alan:snip > > @@ -83,7 +101,7 @@ void intel_pxp_irq_enable(struct intel_pxp *pxp) > > > > void intel_pxp_irq_disable(struct intel_pxp *pxp) > > { > > - struct intel_gt *gt = pxp->ctrl_gt; > > + struct intel_gt *gt = intel_pxp_get_irq_gt(pxp); > > > > AFAICS this functions uses the same 3 cases as above. > > Overall, I am not sure this patch is required. Am I missing something? > alan: context: during development of my initial few revs, i needed to explicitly do that switch-over to the other gt in order to even get the IRQs. (i.e. as if the forcewake didnt wake up the range)... but upon recent retesting it seems to work fine. I guess there must have been a bug somewhere else in my branch. So yes i believe this means we can totally remove this patch
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c b/drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c index 4b8e70caa3ad..9f6e300486b4 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c @@ -44,7 +44,7 @@ static int pxp_terminate_get(void *data, u64 *val) static int pxp_terminate_set(void *data, u64 val) { struct intel_pxp *pxp = data; - struct intel_gt *gt = pxp->ctrl_gt; + struct intel_gt *gt = intel_pxp_get_irq_gt(pxp); if (!intel_pxp_is_active(pxp)) return -ENODEV; diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c b/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c index 91e9622c07d0..3a725397349f 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c @@ -4,10 +4,12 @@ */ #include <linux/workqueue.h> +#include "gt/intel_gt.h" #include "gt/intel_gt_irq.h" #include "gt/intel_gt_regs.h" #include "gt/intel_gt_types.h" +#include "i915_drv.h" #include "i915_irq.h" #include "i915_reg.h" @@ -17,6 +19,22 @@ #include "intel_pxp_types.h" #include "intel_runtime_pm.h" +/** + * intel_pxp_get_irq_gt - Find the correct GT that owns KCR interrupts + * @pxp: pointer to pxp struct + * + * For platforms with a single GT, we return the pxp->ctrl_gt (as expected) + * but for MTL+ that has a media-tile, although the KCR engine is in the + * media-tile (i.e. pxp->ctrl_gt), the IRQ controls are on the root tile. + * In the end, we don't use pxp->ctrl_gt for IRQ, we always return root gt. + */ +struct intel_gt *intel_pxp_get_irq_gt(struct intel_pxp *pxp) +{ + WARN_ON_ONCE(!pxp->ctrl_gt->i915->media_gt && !gt_is_root(pxp->ctrl_gt)); + + return to_gt(pxp->ctrl_gt->i915); +} + /** * intel_pxp_irq_handler - Handles PXP interrupts. * @pxp: pointer to pxp struct @@ -29,7 +47,7 @@ void intel_pxp_irq_handler(struct intel_pxp *pxp, u16 iir) if (GEM_WARN_ON(!intel_pxp_is_enabled(pxp))) return; - gt = pxp->ctrl_gt; + gt = intel_pxp_get_irq_gt(pxp); lockdep_assert_held(gt->irq_lock); @@ -68,7 +86,7 @@ static inline void pxp_irq_reset(struct intel_gt *gt) void intel_pxp_irq_enable(struct intel_pxp *pxp) { - struct intel_gt *gt = pxp->ctrl_gt; + struct intel_gt *gt = intel_pxp_get_irq_gt(pxp); spin_lock_irq(gt->irq_lock); @@ -83,7 +101,7 @@ void intel_pxp_irq_enable(struct intel_pxp *pxp) void intel_pxp_irq_disable(struct intel_pxp *pxp) { - struct intel_gt *gt = pxp->ctrl_gt; + struct intel_gt *gt = intel_pxp_get_irq_gt(pxp); /* * We always need to submit a global termination when we re-enable the diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_irq.h b/drivers/gpu/drm/i915/pxp/intel_pxp_irq.h index 8c292dc86f68..eea87c9eb62b 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_irq.h +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_irq.h @@ -9,6 +9,7 @@ #include <linux/types.h> struct intel_pxp; +struct intel_gt; #define GEN12_DISPLAY_PXP_STATE_TERMINATED_INTERRUPT BIT(1) #define GEN12_DISPLAY_APP_TERMINATED_PER_FW_REQ_INTERRUPT BIT(2) @@ -23,6 +24,8 @@ struct intel_pxp; void intel_pxp_irq_enable(struct intel_pxp *pxp); void intel_pxp_irq_disable(struct intel_pxp *pxp); void intel_pxp_irq_handler(struct intel_pxp *pxp, u16 iir); +struct intel_gt *intel_pxp_get_irq_gt(struct intel_pxp *pxp); + #else static inline void intel_pxp_irq_handler(struct intel_pxp *pxp, u16 iir) { @@ -35,6 +38,11 @@ static inline void intel_pxp_irq_enable(struct intel_pxp *pxp) static inline void intel_pxp_irq_disable(struct intel_pxp *pxp) { } + +static inline struct intel_gt *intel_pxp_get_irq_gt(struct intel_pxp *pxp) +{ + return NULL; +} #endif #endif /* __INTEL_PXP_IRQ_H__ */
Despite KCR subsystem being in the media-tile (close to the GSC-CS), the IRQ controls for it are on GT-0 with other global IRQ controls. Thus, add a helper for KCR hw interrupt enable/disable functions to get the correct gt structure (for uncore) for MTL. In the helper, we get GT-0's handle for uncore when touching IRQ registers despite the pxp->ctrl_gt being the media-tile. No difference for legacy of course. Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com> --- drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c | 2 +- drivers/gpu/drm/i915/pxp/intel_pxp_irq.c | 24 +++++++++++++++++--- drivers/gpu/drm/i915/pxp/intel_pxp_irq.h | 8 +++++++ 3 files changed, 30 insertions(+), 4 deletions(-)