| Message ID | 20230410033526.31708-2-liweiwei@iscas.ac.cn (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | target/riscv: Separate implicitly-enabled and explicitly-enabled extensions | expand |
On 4/10/23 00:35, Weiwei Li wrote: > Move multi-letter extensions that may implicitly enabled from misa.EXT > alone to prepare for following separation of implicitly enabled and > explicitly enabled extensions. > > Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> > Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> > --- Regardless of what we end up doing with patch 2 I believe this is a good separation to have. Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> > target/riscv/cpu.c | 56 +++++++++++++++++++++++++--------------------- > 1 file changed, 31 insertions(+), 25 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index cb68916fce..abb65d41b1 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -809,6 +809,35 @@ static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) > } > } > > +static void set_implicit_extensions_from_ext(RISCVCPU *cpu) > +{ > + > + /* The V vector extension depends on the Zve64d extension */ > + if (cpu->cfg.ext_v) { > + cpu->cfg.ext_zve64d = true; > + } > + > + /* The Zve64d extension depends on the Zve64f extension */ > + if (cpu->cfg.ext_zve64d) { > + cpu->cfg.ext_zve64f = true; > + } > + > + /* The Zve64f extension depends on the Zve32f extension */ > + if (cpu->cfg.ext_zve64f) { > + cpu->cfg.ext_zve32f = true; > + } > + > + if (cpu->cfg.ext_c) { > + cpu->cfg.ext_zca = true; > + if (cpu->cfg.ext_f && cpu->env.misa_mxl_max == MXL_RV32) { > + cpu->cfg.ext_zcf = true; > + } > + if (cpu->cfg.ext_d) { > + cpu->cfg.ext_zcd = true; > + } > + } > +} > + > /* > * Check consistency between chosen extensions while setting > * cpu->cfg accordingly, doing a set_misa() in the end. > @@ -833,6 +862,8 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) > cpu->cfg.ext_ifencei = true; > } > > + set_implicit_extensions_from_ext(cpu); > + > if (cpu->cfg.ext_i && cpu->cfg.ext_e) { > error_setg(errp, > "I and E extensions are incompatible"); > @@ -886,21 +917,6 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) > return; > } > > - /* The V vector extension depends on the Zve64d extension */ > - if (cpu->cfg.ext_v) { > - cpu->cfg.ext_zve64d = true; > - } > - > - /* The Zve64d extension depends on the Zve64f extension */ > - if (cpu->cfg.ext_zve64d) { > - cpu->cfg.ext_zve64f = true; > - } > - > - /* The Zve64f extension depends on the Zve32f extension */ > - if (cpu->cfg.ext_zve64f) { > - cpu->cfg.ext_zve32f = true; > - } > - > if (cpu->cfg.ext_zve64d && !cpu->cfg.ext_d) { > error_setg(errp, "Zve64d/V extensions require D extension"); > return; > @@ -956,16 +972,6 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) > } > } > > - if (cpu->cfg.ext_c) { > - cpu->cfg.ext_zca = true; > - if (cpu->cfg.ext_f && env->misa_mxl_max == MXL_RV32) { > - cpu->cfg.ext_zcf = true; > - } > - if (cpu->cfg.ext_d) { > - cpu->cfg.ext_zcd = true; > - } > - } > - > if (env->misa_mxl_max != MXL_RV32 && cpu->cfg.ext_zcf) { > error_setg(errp, "Zcf extension is only relevant to RV32"); > return;
On Mon, Apr 10, 2023 at 1:36 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote: > > Move multi-letter extensions that may implicitly enabled from misa.EXT > alone to prepare for following separation of implicitly enabled and > explicitly enabled extensions. > > Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> > Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/cpu.c | 56 +++++++++++++++++++++++++--------------------- > 1 file changed, 31 insertions(+), 25 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index cb68916fce..abb65d41b1 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -809,6 +809,35 @@ static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) > } > } > > +static void set_implicit_extensions_from_ext(RISCVCPU *cpu) > +{ > + > + /* The V vector extension depends on the Zve64d extension */ > + if (cpu->cfg.ext_v) { > + cpu->cfg.ext_zve64d = true; > + } > + > + /* The Zve64d extension depends on the Zve64f extension */ > + if (cpu->cfg.ext_zve64d) { > + cpu->cfg.ext_zve64f = true; > + } > + > + /* The Zve64f extension depends on the Zve32f extension */ > + if (cpu->cfg.ext_zve64f) { > + cpu->cfg.ext_zve32f = true; > + } > + > + if (cpu->cfg.ext_c) { > + cpu->cfg.ext_zca = true; > + if (cpu->cfg.ext_f && cpu->env.misa_mxl_max == MXL_RV32) { > + cpu->cfg.ext_zcf = true; > + } > + if (cpu->cfg.ext_d) { > + cpu->cfg.ext_zcd = true; > + } > + } > +} > + > /* > * Check consistency between chosen extensions while setting > * cpu->cfg accordingly, doing a set_misa() in the end. > @@ -833,6 +862,8 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) > cpu->cfg.ext_ifencei = true; > } > > + set_implicit_extensions_from_ext(cpu); > + > if (cpu->cfg.ext_i && cpu->cfg.ext_e) { > error_setg(errp, > "I and E extensions are incompatible"); > @@ -886,21 +917,6 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) > return; > } > > - /* The V vector extension depends on the Zve64d extension */ > - if (cpu->cfg.ext_v) { > - cpu->cfg.ext_zve64d = true; > - } > - > - /* The Zve64d extension depends on the Zve64f extension */ > - if (cpu->cfg.ext_zve64d) { > - cpu->cfg.ext_zve64f = true; > - } > - > - /* The Zve64f extension depends on the Zve32f extension */ > - if (cpu->cfg.ext_zve64f) { > - cpu->cfg.ext_zve32f = true; > - } > - > if (cpu->cfg.ext_zve64d && !cpu->cfg.ext_d) { > error_setg(errp, "Zve64d/V extensions require D extension"); > return; > @@ -956,16 +972,6 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) > } > } > > - if (cpu->cfg.ext_c) { > - cpu->cfg.ext_zca = true; > - if (cpu->cfg.ext_f && env->misa_mxl_max == MXL_RV32) { > - cpu->cfg.ext_zcf = true; > - } > - if (cpu->cfg.ext_d) { > - cpu->cfg.ext_zcd = true; > - } > - } > - > if (env->misa_mxl_max != MXL_RV32 && cpu->cfg.ext_zcf) { > error_setg(errp, "Zcf extension is only relevant to RV32"); > return; > -- > 2.25.1 > >
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index cb68916fce..abb65d41b1 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -809,6 +809,35 @@ static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) } } +static void set_implicit_extensions_from_ext(RISCVCPU *cpu) +{ + + /* The V vector extension depends on the Zve64d extension */ + if (cpu->cfg.ext_v) { + cpu->cfg.ext_zve64d = true; + } + + /* The Zve64d extension depends on the Zve64f extension */ + if (cpu->cfg.ext_zve64d) { + cpu->cfg.ext_zve64f = true; + } + + /* The Zve64f extension depends on the Zve32f extension */ + if (cpu->cfg.ext_zve64f) { + cpu->cfg.ext_zve32f = true; + } + + if (cpu->cfg.ext_c) { + cpu->cfg.ext_zca = true; + if (cpu->cfg.ext_f && cpu->env.misa_mxl_max == MXL_RV32) { + cpu->cfg.ext_zcf = true; + } + if (cpu->cfg.ext_d) { + cpu->cfg.ext_zcd = true; + } + } +} + /* * Check consistency between chosen extensions while setting * cpu->cfg accordingly, doing a set_misa() in the end. @@ -833,6 +862,8 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) cpu->cfg.ext_ifencei = true; } + set_implicit_extensions_from_ext(cpu); + if (cpu->cfg.ext_i && cpu->cfg.ext_e) { error_setg(errp, "I and E extensions are incompatible"); @@ -886,21 +917,6 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) return; } - /* The V vector extension depends on the Zve64d extension */ - if (cpu->cfg.ext_v) { - cpu->cfg.ext_zve64d = true; - } - - /* The Zve64d extension depends on the Zve64f extension */ - if (cpu->cfg.ext_zve64d) { - cpu->cfg.ext_zve64f = true; - } - - /* The Zve64f extension depends on the Zve32f extension */ - if (cpu->cfg.ext_zve64f) { - cpu->cfg.ext_zve32f = true; - } - if (cpu->cfg.ext_zve64d && !cpu->cfg.ext_d) { error_setg(errp, "Zve64d/V extensions require D extension"); return; @@ -956,16 +972,6 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) } } - if (cpu->cfg.ext_c) { - cpu->cfg.ext_zca = true; - if (cpu->cfg.ext_f && env->misa_mxl_max == MXL_RV32) { - cpu->cfg.ext_zcf = true; - } - if (cpu->cfg.ext_d) { - cpu->cfg.ext_zcd = true; - } - } - if (env->misa_mxl_max != MXL_RV32 && cpu->cfg.ext_zcf) { error_setg(errp, "Zcf extension is only relevant to RV32"); return;