diff mbox series

[v3,2/3] target/riscv: Use PRV_RESERVED instead of PRV_H

Message ID 20230407014743.18779-3-liweiwei@iscas.ac.cn (mailing list archive)
State New, archived
Headers show
Series target/riscv: Fix mstatus.MPP related support | expand

Commit Message

Weiwei Li April 7, 2023, 1:47 a.m. UTC 
PRV_H has no real meaning, but just a reserved privilege mode currently.

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
 target/riscv/cpu.h       | 2 +-
 target/riscv/cpu_bits.h  | 2 +-
 target/riscv/gdbstub.c   | 2 +-
 target/riscv/op_helper.c | 2 +-
 4 files changed, 4 insertions(+), 4 deletions(-)

Comments

Richard Henderson April 7, 2023, 4:31 p.m. UTC | #1 
On 4/6/23 18:47, Weiwei Li wrote:
> PRV_H has no real meaning, but just a reserved privilege mode currently.
> 
> Signed-off-by: Weiwei Li<liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang<wangjunqiang@iscas.ac.cn>
> ---
>   target/riscv/cpu.h       | 2 +-
>   target/riscv/cpu_bits.h  | 2 +-
>   target/riscv/gdbstub.c   | 2 +-
>   target/riscv/op_helper.c | 2 +-
>   4 files changed, 4 insertions(+), 4 deletions(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Thanks!


r~
Alistair Francis April 11, 2023, 1:49 a.m. UTC | #2 
On Fri, Apr 7, 2023 at 11:49 AM Weiwei Li <liweiwei@iscas.ac.cn> wrote:
>
> PRV_H has no real meaning, but just a reserved privilege mode currently.
>
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/cpu.h       | 2 +-
>  target/riscv/cpu_bits.h  | 2 +-
>  target/riscv/gdbstub.c   | 2 +-
>  target/riscv/op_helper.c | 2 +-
>  4 files changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index cbf3de2708..4af8ebc558 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -699,7 +699,7 @@ static inline RISCVMXL cpu_recompute_xl(CPURISCVState *env)
>          case PRV_U:
>              xl = get_field(env->mstatus, MSTATUS64_UXL);
>              break;
> -        default: /* PRV_S | PRV_H */
> +        default: /* PRV_S */
>              xl = get_field(env->mstatus, MSTATUS64_SXL);
>              break;
>          }
> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> index 101702cb4a..a16bfaf43f 100644
> --- a/target/riscv/cpu_bits.h
> +++ b/target/riscv/cpu_bits.h
> @@ -608,7 +608,7 @@ typedef enum {
>  /* Privilege modes */
>  #define PRV_U 0
>  #define PRV_S 1
> -#define PRV_H 2 /* Reserved */
> +#define PRV_RESERVED 2
>  #define PRV_M 3
>
>  /* RV32 satp CSR field masks */
> diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
> index fa537aed74..524bede865 100644
> --- a/target/riscv/gdbstub.c
> +++ b/target/riscv/gdbstub.c
> @@ -203,7 +203,7 @@ static int riscv_gdb_set_virtual(CPURISCVState *cs, uint8_t *mem_buf, int n)
>      if (n == 0) {
>  #ifndef CONFIG_USER_ONLY
>          cs->priv = ldtul_p(mem_buf) & 0x3;
> -        if (cs->priv == PRV_H) {
> +        if (cs->priv == PRV_RESERVED) {
>              cs->priv = PRV_S;
>          }
>  #endif
> diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
> index b8a03afebb..bd21c6eeef 100644
> --- a/target/riscv/op_helper.c
> +++ b/target/riscv/op_helper.c
> @@ -141,7 +141,7 @@ static void check_zicbo_envcfg(CPURISCVState *env, target_ulong envbits,
>      }
>
>      if (env->virt_enabled &&
> -        (((env->priv < PRV_H) && !get_field(env->henvcfg, envbits)) ||
> +        (((env->priv <= PRV_S) && !get_field(env->henvcfg, envbits)) ||
>           ((env->priv < PRV_S) && !get_field(env->senvcfg, envbits)))) {
>          riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, ra);
>      }
> --
> 2.25.1
>
>
diff mbox series

Patch

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index cbf3de2708..4af8ebc558 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -699,7 +699,7 @@  static inline RISCVMXL cpu_recompute_xl(CPURISCVState *env)
         case PRV_U:
             xl = get_field(env->mstatus, MSTATUS64_UXL);
             break;
-        default: /* PRV_S | PRV_H */
+        default: /* PRV_S */
             xl = get_field(env->mstatus, MSTATUS64_SXL);
             break;
         }
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 101702cb4a..a16bfaf43f 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -608,7 +608,7 @@  typedef enum {
 /* Privilege modes */
 #define PRV_U 0
 #define PRV_S 1
-#define PRV_H 2 /* Reserved */
+#define PRV_RESERVED 2
 #define PRV_M 3
 
 /* RV32 satp CSR field masks */
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index fa537aed74..524bede865 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -203,7 +203,7 @@  static int riscv_gdb_set_virtual(CPURISCVState *cs, uint8_t *mem_buf, int n)
     if (n == 0) {
 #ifndef CONFIG_USER_ONLY
         cs->priv = ldtul_p(mem_buf) & 0x3;
-        if (cs->priv == PRV_H) {
+        if (cs->priv == PRV_RESERVED) {
             cs->priv = PRV_S;
         }
 #endif
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index b8a03afebb..bd21c6eeef 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -141,7 +141,7 @@  static void check_zicbo_envcfg(CPURISCVState *env, target_ulong envbits,
     }
 
     if (env->virt_enabled &&
-        (((env->priv < PRV_H) && !get_field(env->henvcfg, envbits)) ||
+        (((env->priv <= PRV_S) && !get_field(env->henvcfg, envbits)) ||
          ((env->priv < PRV_S) && !get_field(env->senvcfg, envbits)))) {
         riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, ra);
     }