Message ID | 20230330063450.2289058-1-joychakr@google.com (mailing list archive) |
---|---|
Headers | show |
Series | spi: dw: DW SPI DMA Driver updates | expand |
Cc+=Andy On Thu, Mar 30, 2023 at 06:34:48AM +0000, Joy Chakraborty wrote: > This Patch series adds support for 32 bits per word trasfers using DMA > and some defensive checks around dma controller capabilities. > --- > V1 Changes : Add support for AxSize=4 bytes to support 32bits/word. > --- > V1->V2 Changes : Add dma capability check to make sure address widths > are supported. > --- > V2->V3 Changes : Split changes , add DMA direction check and other > cosmetic chnages. > --- > V3->V4 Changes : Fix Sparce Warning > | Reported-by: kernel test robot <lkp@intel.com> > | Link: https://lore.kernel.org/oe-kbuild-all/202303270715.w9sMJhIh-lkp@intel.com/ > --- > V4->V5 Changes : Preserve reverse xmas Tree order, move direction > check before initalisation of further capabilities, remove zero > initialisations, remove error OR'ing. The series looks good to me now. Though if I were you I would have split up the last patch into two ones. Anyway I tested the patchset on Baikal-T1 SoC with DW APB SSI 3.22b + DW DMAC 2.18b and looped back SPI-interface. So feel free to add: Tested-by: Serge Semin <fancer.lancer@gmail.com> Reviewed-by: Serge Semin <fancer.lancer@gmail.com> @Andy, anything to add from your side? @Mark, if you are ok with the series content please merge in. -Serge(y) > --- > > Joy Chakraborty (2): > spi: dw: Add 32 bpw support to DW DMA Controller > spi: dw: Add dma controller capability checks > > drivers/spi/spi-dw-dma.c | 70 ++++++++++++++++++++++++++++++++-------- > drivers/spi/spi-dw.h | 1 + > 2 files changed, 57 insertions(+), 14 deletions(-) > > -- > 2.40.0.423.gd6c402a77b-goog >
On Tue, Apr 11, 2023 at 08:12:33AM +0300, Serge Semin wrote: > Cc+=Andy Thank for Cc'ing me. I'll go through individual patches and give my comments if any. > On Thu, Mar 30, 2023 at 06:34:48AM +0000, Joy Chakraborty wrote: > > This Patch series adds support for 32 bits per word trasfers using DMA > > and some defensive checks around dma controller capabilities. > > --- > > V1 Changes : Add support for AxSize=4 bytes to support 32bits/word. > > --- > > V1->V2 Changes : Add dma capability check to make sure address widths > > are supported. > > --- > > V2->V3 Changes : Split changes , add DMA direction check and other > > cosmetic chnages. > > --- > > V3->V4 Changes : Fix Sparce Warning > > | Reported-by: kernel test robot <lkp@intel.com> > > | Link: https://lore.kernel.org/oe-kbuild-all/202303270715.w9sMJhIh-lkp@intel.com/ > > --- > > V4->V5 Changes : Preserve reverse xmas Tree order, move direction > > check before initalisation of further capabilities, remove zero > > initialisations, remove error OR'ing. > > The series looks good to me now. Though if I were you I would have > split up the last patch into two ones. > > Anyway I tested the patchset on Baikal-T1 SoC with DW APB SSI 3.22b + > DW DMAC 2.18b and looped back SPI-interface. So feel free to add: > Tested-by: Serge Semin <fancer.lancer@gmail.com> > Reviewed-by: Serge Semin <fancer.lancer@gmail.com> > > @Andy, anything to add from your side? > @Mark, if you are ok with the series content please merge in.