diff mbox series

[v2,07/19] arm64: cpufeature: add Permission Indirection Extension cpucap

Message ID 20230413110513.243326-8-joey.gouly@arm.com (mailing list archive)
State New, archived
Headers show
Series Permission Indirection Extension | expand

Commit Message

Joey Gouly April 13, 2023, 11:05 a.m. UTC 
This indicates if the system supports PIE. This is a CPUCAP_BOOT_CPU_FEATURE
as the boot CPU will enable PIE if it has it, so secondary CPUs must also
have this feature.

Signed-off-by: Joey Gouly <joey.gouly@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
---
 arch/arm64/kernel/cpufeature.c | 11 +++++++++++
 arch/arm64/tools/cpucaps       |  1 +
 2 files changed, 12 insertions(+)

Comments

Mark Brown April 13, 2023, 11:30 a.m. UTC | #1 
On Thu, Apr 13, 2023 at 12:05:01PM +0100, Joey Gouly wrote:
> This indicates if the system supports PIE. This is a CPUCAP_BOOT_CPU_FEATURE
> as the boot CPU will enable PIE if it has it, so secondary CPUs must also
> have this feature.

Reviewed-by: Mark Brown <broonie@kernel.org>

> +	{
> +		.desc = "Permission Indirection Extension (PIE)",
> +		.capability = ARM64_HAS_PIE,
> +		.type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
> +		.sys_reg = SYS_ID_AA64MMFR3_EL1,
> +		.sign = FTR_UNSIGNED,
> +		.field_pos = ID_AA64MMFR3_EL1_S1PIE_SHIFT,
> +		.field_width = 4,
> +		.min_field_value = ID_AA64MMFR3_EL1_S1PIE_IMP,
> +		.matches = has_cpuid_feature,
> +	},

It might avoid some future confusion to label this as being stage 1, but
that's just bikeshedding.
diff mbox series

Patch

diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 6944d8bbb17c..acbc21963128 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -2793,6 +2793,17 @@  static const struct arm64_cpu_capabilities arm64_features[] = {
 		.min_field_value = ID_AA64MMFR3_EL1_TCRX_IMP,
 		.matches = has_cpuid_feature,
 	},
+	{
+		.desc = "Permission Indirection Extension (PIE)",
+		.capability = ARM64_HAS_PIE,
+		.type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
+		.sys_reg = SYS_ID_AA64MMFR3_EL1,
+		.sign = FTR_UNSIGNED,
+		.field_pos = ID_AA64MMFR3_EL1_S1PIE_SHIFT,
+		.field_width = 4,
+		.min_field_value = ID_AA64MMFR3_EL1_S1PIE_IMP,
+		.matches = has_cpuid_feature,
+	},
 	{},
 };
 
diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps
index 5859b9ee7444..c4c4c59882b8 100644
--- a/arch/arm64/tools/cpucaps
+++ b/arch/arm64/tools/cpucaps
@@ -37,6 +37,7 @@  HAS_NESTED_VIRT
 HAS_NO_FPSIMD
 HAS_NO_HW_PREFETCH
 HAS_PAN
+HAS_PIE
 HAS_RAS_EXTN
 HAS_RNG
 HAS_SB