diff mbox series

arm64: dts: rockchip: Add pinctrl gpio-ranges for rk356x

Message ID 20230413144316.4247-1-inindev@gmail.com (mailing list archive)
State New, archived
Headers show
Series arm64: dts: rockchip: Add pinctrl gpio-ranges for rk356x | expand

Commit Message

John Clark April 13, 2023, 2:43 p.m. UTC 
Add gpio-range properties to the pinctrl gpio nodes in rk356x.dtsi

Signed-off-by: John Clark <inindev@gmail.com>
---
 arch/arm64/boot/dts/rockchip/rk356x.dtsi | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

Comments

Krzysztof Kozlowski April 13, 2023, 4:11 p.m. UTC | #1 
On 13/04/2023 16:43, John Clark wrote:
> Add gpio-range properties to the pinctrl gpio nodes in rk356x.dtsi
> 
> Signed-off-by: John Clark <inindev@gmail.com>
> ---
>  arch/arm64/boot/dts/rockchip/rk356x.dtsi | 7 ++++++-
>  1 file changed, 6 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
> index 802fcc96384e..793dbcb981dc 100644
> --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
> @@ -1796,11 +1796,11 @@ usb2phy1_otg: otg-port {
>  
>  	pinctrl: pinctrl {
>  		compatible = "rockchip,rk3568-pinctrl";
> +		ranges;
>  		rockchip,grf = <&grf>;
>  		rockchip,pmu = <&pmugrf>;
>  		#address-cells = <2>;
>  		#size-cells = <2>;
> -		ranges;

Not related to your patch.

Best regards,
Krzysztof
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
index 802fcc96384e..793dbcb981dc 100644
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
@@ -1796,11 +1796,11 @@  usb2phy1_otg: otg-port {
 
 	pinctrl: pinctrl {
 		compatible = "rockchip,rk3568-pinctrl";
+		ranges;
 		rockchip,grf = <&grf>;
 		rockchip,pmu = <&pmugrf>;
 		#address-cells = <2>;
 		#size-cells = <2>;
-		ranges;
 
 		gpio0: gpio@fdd60000 {
 			compatible = "rockchip,gpio-bank";
@@ -1808,6 +1808,7 @@  gpio0: gpio@fdd60000 {
 			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&pmucru PCLK_GPIO0>, <&pmucru DBCLK_GPIO0>;
 			gpio-controller;
+			gpio-ranges = <&pinctrl 0 0 32>;
 			#gpio-cells = <2>;
 			interrupt-controller;
 			#interrupt-cells = <2>;
@@ -1819,6 +1820,7 @@  gpio1: gpio@fe740000 {
 			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
 			gpio-controller;
+			gpio-ranges = <&pinctrl 0 32 32>;
 			#gpio-cells = <2>;
 			interrupt-controller;
 			#interrupt-cells = <2>;
@@ -1830,6 +1832,7 @@  gpio2: gpio@fe750000 {
 			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
 			gpio-controller;
+			gpio-ranges = <&pinctrl 0 64 32>;
 			#gpio-cells = <2>;
 			interrupt-controller;
 			#interrupt-cells = <2>;
@@ -1841,6 +1844,7 @@  gpio3: gpio@fe760000 {
 			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
 			gpio-controller;
+			gpio-ranges = <&pinctrl 0 96 32>;
 			#gpio-cells = <2>;
 			interrupt-controller;
 			#interrupt-cells = <2>;
@@ -1852,6 +1856,7 @@  gpio4: gpio@fe770000 {
 			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
 			gpio-controller;
+			gpio-ranges = <&pinctrl 0 128 32>;
 			#gpio-cells = <2>;
 			interrupt-controller;
 			#interrupt-cells = <2>;