diff mbox series

[v2,18/19] arm64: Document boot requirements for PIE

Message ID 20230413110513.243326-19-joey.gouly@arm.com (mailing list archive)
State New, archived
Headers show
Series Permission Indirection Extension | expand

Commit Message

Joey Gouly April 13, 2023, 11:05 a.m. UTC 
Features PIE and TCR2 introduce new registers, update the trap requirements
for these features.

Signed-off-by: Joey Gouly <joey.gouly@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Mark Brown <broonie@kernel.org>
---
 Documentation/arm64/booting.rst | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

Comments

Mark Brown April 13, 2023, 11:45 a.m. UTC | #1 
On Thu, Apr 13, 2023 at 12:05:12PM +0100, Joey Gouly wrote:

> Features PIE and TCR2 introduce new registers, update the trap requirements
> for these features.

Reviewed-by: Mark Brown <broonie@kernel.org>

We could also do S2 and SxPOR while we're at it, but you could say the
same for any feature so it shoudn't be a blocker.
Catalin Marinas April 13, 2023, 4:45 p.m. UTC | #2 
On Thu, Apr 13, 2023 at 12:05:12PM +0100, Joey Gouly wrote:
> Features PIE and TCR2 introduce new registers, update the trap requirements
> for these features.
> 
> Signed-off-by: Joey Gouly <joey.gouly@arm.com>
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Will Deacon <will@kernel.org>
> Cc: Mark Brown <broonie@kernel.org>

Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
diff mbox series

Patch

diff --git a/Documentation/arm64/booting.rst b/Documentation/arm64/booting.rst
index ffeccdd6bdac..babbf36f0ce2 100644
--- a/Documentation/arm64/booting.rst
+++ b/Documentation/arm64/booting.rst
@@ -379,6 +379,32 @@  Before jumping into the kernel, the following conditions must be met:
 
     - SMCR_EL2.EZT0 (bit 30) must be initialised to 0b1.
 
+  For CPUs with the Extended Translation Control Register feature (FEAT_TCR2):
+
+  - If EL3 is present:
+
+    - SCR_EL3.TCR2En (bit 43) must be initialised to 0b1.
+
+ - If the kernel is entered at EL1 and EL2 is present:
+
+    - HCRX_EL2.TCR2En (bit 14) must be initialised to 0b1.
+
+  For CPUs with the Stage 1 Permission Indirection Extension feature (FEAT_S1PIE):
+
+  - If EL3 is present:
+
+    - SCR_EL3.PIEn (bit 45) must be initialised to 0b1.
+
+  - If the kernel is entered at EL1 and EL2 is present:
+
+    - HFGRTR_EL2.nPIR_EL1 (bit 58) must be initialised to 0b1.
+
+    - HFGWTR_EL2.nPIR_EL1 (bit 58) must be initialised to 0b1.
+
+    - HFGRTR_EL2.nPIRE0_EL1 (bit 57) must be initialised to 0b1.
+
+    - HFGRWR_EL2.nPIRE0_EL1 (bit 57) must be initialised to 0b1.
+
 The requirements described above for CPU mode, caches, MMUs, architected
 timers, coherency and system registers apply to all CPUs.  All CPUs must
 enter the kernel in the same exception level.  Where the values documented