diff mbox series

[v2,2/2] arm64: dts: rockchip: rk3588: add MSI support

Message ID 20230417150038.51698-3-sebastian.reichel@collabora.com (mailing list archive)
State New, archived
Headers show
Series Add Rockchip RK3588 GIC ITS support | expand

Commit Message

Sebastian Reichel April 17, 2023, 3 p.m. UTC 
Add the two Interrupt Translation Service (ITS) IPs that are part of the
GIC-600, which are required for message signalled interrupts (MSI). This
is required for PCIe, which fully relies on MSI for interrupts.

Enabling the ITS nodes requires an operating system, that has a
workaround for Rockchip errata #3588001 (GIC600 can not support
shareable attribute).

Co-developed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
 arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

Comments

Marc Zyngier April 17, 2023, 4:39 p.m. UTC | #1 
On Mon, 17 Apr 2023 16:00:38 +0100,
Sebastian Reichel <sebastian.reichel@collabora.com> wrote:
> 
> Add the two Interrupt Translation Service (ITS) IPs that are part of the
> GIC-600, which are required for message signalled interrupts (MSI). This
> is required for PCIe, which fully relies on MSI for interrupts.
> 
> Enabling the ITS nodes requires an operating system, that has a
> workaround for Rockchip errata #3588001 (GIC600 can not support
> shareable attribute).

$SUBJECT is inaccurate. This adds the descriptions of the ITSs, but
doesn't wire any MSI support at all (nobody even refers these
nodes, so the whole thing is pretty pointless).

	M.
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
index 2124c654f665..62204b96b0b4 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
@@ -1741,7 +1741,24 @@  gic: interrupt-controller@fe600000 {
 		mbi-alias = <0x0 0xfe610000>;
 		mbi-ranges = <424 56>;
 		msi-controller;
+		ranges;
+		#address-cells = <2>;
 		#interrupt-cells = <4>;
+		#size-cells = <2>;
+
+		its0: msi-controller@fe640000 {
+			compatible = "arm,gic-v3-its";
+			msi-controller;
+			#msi-cells = <1>;
+			reg = <0x0 0xfe640000 0x0 0x20000>;
+		};
+
+		its1: msi-controller@fe660000 {
+			compatible = "arm,gic-v3-its";
+			msi-controller;
+			#msi-cells = <1>;
+			reg = <0x0 0xfe660000 0x0 0x20000>;
+		};
 
 		ppi-partitions {
 			ppi_partition0: interrupt-partition-0 {