| Message ID | 20230414024157.53203-6-xingyu.wu@starfivetech.com (mailing list archive) |
|---|---|
| State | Superseded, archived |
| Headers | show |
| Series | Add PLL clocks driver for StarFive JH7110 SoC | expand |
On Fri, 14 Apr 2023 10:41:55 +0800, Xingyu Wu wrote: > From: William Qiu <william.qiu@starfivetech.com> > > Add documentation to describe StarFive System Controller Registers. > > Signed-off-by: William Qiu <william.qiu@starfivetech.com> > --- > .../soc/starfive/starfive,jh7110-syscon.yaml | 58 +++++++++++++++++++ > MAINTAINERS | 6 ++ > 2 files changed, 64 insertions(+) > create mode 100644 Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' on your patch (DT_CHECKER_FLAGS is new in v5.13): yamllint warnings/errors: dtschema/dtc warnings/errors: ./Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml: Unable to find schema file matching $id: http://devicetree.org/schemas/clock/starfive,jh7110-pll.yaml doc reference errors (make refcheckdocs): See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20230414024157.53203-6-xingyu.wu@starfivetech.com The base for the series is generally the latest rc1. A different dependency should be noted in *this* patch. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit after running the above command yourself. Note that DT_SCHEMA_FILES can be set to your schema file to speed up checking your schema. However, it must be unset to test all examples with your schema.
On 2023/4/14 20:37, Rob Herring wrote: > > On Fri, 14 Apr 2023 10:41:55 +0800, Xingyu Wu wrote: >> From: William Qiu <william.qiu@starfivetech.com> >> >> Add documentation to describe StarFive System Controller Registers. >> >> Signed-off-by: William Qiu <william.qiu@starfivetech.com> >> --- >> .../soc/starfive/starfive,jh7110-syscon.yaml | 58 +++++++++++++++++++ >> MAINTAINERS | 6 ++ >> 2 files changed, 64 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml >> > > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' > on your patch (DT_CHECKER_FLAGS is new in v5.13): > > yamllint warnings/errors: > > dtschema/dtc warnings/errors: > ./Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml: Unable to find schema file matching $id: http://devicetree.org/schemas/clock/starfive,jh7110-pll.yaml > > doc reference errors (make refcheckdocs): > > See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20230414024157.53203-6-xingyu.wu@starfivetech.com > > The base for the series is generally the latest rc1. A different dependency > should be noted in *this* patch. > > If you already ran 'make dt_binding_check' and didn't see the above > error(s), then make sure 'yamllint' is installed and dt-schema is up to > date: > > pip3 install dtschema --upgrade > > Please check and re-submit after running the above command yourself. Note > that DT_SCHEMA_FILES can be set to your schema file to speed up checking > your schema. However, it must be unset to test all examples with your schema. > I have updated yamllint and dtschema, and tested it and didn't see this error. I asked william and also didn't see this. This error says the file: http://devicetree.org/schemas/clock/starfive,jh7110-pll.yaml was not found. This file is added in patch 1 but patch 1 should be applied after these patchset about JH7110 basic clock drivers. I don't know if that's the reason. Best regards, Xingyu Wu
On Mon, Apr 17, 2023 at 03:43:48PM +0800, Xingyu Wu wrote: > On 2023/4/14 20:37, Rob Herring wrote: > > > > On Fri, 14 Apr 2023 10:41:55 +0800, Xingyu Wu wrote: > >> From: William Qiu <william.qiu@starfivetech.com> > >> > >> Add documentation to describe StarFive System Controller Registers. > >> > >> Signed-off-by: William Qiu <william.qiu@starfivetech.com> > >> --- > >> .../soc/starfive/starfive,jh7110-syscon.yaml | 58 +++++++++++++++++++ > >> MAINTAINERS | 6 ++ > >> 2 files changed, 64 insertions(+) > >> create mode 100644 Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml > >> > > > > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' > > on your patch (DT_CHECKER_FLAGS is new in v5.13): > > > > yamllint warnings/errors: > > > > dtschema/dtc warnings/errors: > > ./Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml: Unable to find schema file matching $id: http://devicetree.org/schemas/clock/starfive,jh7110-pll.yaml > > > > doc reference errors (make refcheckdocs): > > > > See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20230414024157.53203-6-xingyu.wu@starfivetech.com > > > > The base for the series is generally the latest rc1. A different dependency > > should be noted in *this* patch. > > > > If you already ran 'make dt_binding_check' and didn't see the above > > error(s), then make sure 'yamllint' is installed and dt-schema is up to > > date: > > > > pip3 install dtschema --upgrade > > > > Please check and re-submit after running the above command yourself. Note > > that DT_SCHEMA_FILES can be set to your schema file to speed up checking > > your schema. However, it must be unset to test all examples with your schema. > > > > I have updated yamllint and dtschema, and tested it and didn't see this error. > I asked william and also didn't see this. This error says the file: > http://devicetree.org/schemas/clock/starfive,jh7110-pll.yaml was not found. > This file is added in patch 1 but patch 1 should be applied after these patchset > about JH7110 basic clock drivers. I don't know if that's the reason. Yes, patch 1 could not be applied[1]. Rob [1] https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20230414024157.53203-2-xingyu.wu@starfivetech.com/
On Fri, 14 Apr 2023 10:41:55 +0800, Xingyu Wu wrote: > From: William Qiu <william.qiu@starfivetech.com> > > Add documentation to describe StarFive System Controller Registers. > > Signed-off-by: William Qiu <william.qiu@starfivetech.com> > --- > .../soc/starfive/starfive,jh7110-syscon.yaml | 58 +++++++++++++++++++ > MAINTAINERS | 6 ++ > 2 files changed, 64 insertions(+) > create mode 100644 Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml > Reviewed-by: Rob Herring <robh@kernel.org>
On Fri, Apr 14, 2023 at 10:41:55AM +0800, Xingyu Wu wrote: > From: William Qiu <william.qiu@starfivetech.com> > > Add documentation to describe StarFive System Controller Registers. > > Signed-off-by: William Qiu <william.qiu@starfivetech.com> > --- > .../soc/starfive/starfive,jh7110-syscon.yaml | 58 +++++++++++++++++++ > MAINTAINERS | 6 ++ > 2 files changed, 64 insertions(+) > create mode 100644 Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml > > diff --git a/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml > new file mode 100644 > index 000000000000..de086e74a229 > --- /dev/null > +++ b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml > @@ -0,0 +1,58 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/soc/starfive/starfive,jh7110-syscon.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: StarFive JH7110 SoC system controller > + > +maintainers: > + - William Qiu <william.qiu@starfivetech.com> > + > +description: | > + The StarFive JH7110 SoC system controller provides register information such > + as offset, mask and shift to configure related modules such as MMC and PCIe. > + > +properties: > + compatible: > + oneOf: > + - items: > + - enum: > + - starfive,jh7110-aon-syscon > + - starfive,jh7110-sys-syscon > + - const: syscon > + - const: simple-mfd > + - items: > + - const: starfive,jh7110-stg-syscon > + - const: syscon > + > + reg: > + maxItems: 1 > + > + clock-controller: > + $ref: /schemas/clock/starfive,jh7110-pll.yaml# > + type: object > + > + power-controller: > + $ref: /schemas/power/starfive,jh7110-pmu.yaml# > + type: object My plan was to grab this patch after the merge window, but there's been some back and forth [1] about what exactly should be a power-controller here. Given the merge window is open & I know Emil wants to look at the various clock bits for the JH7110, I don't think there's a pressing need for you to do anything here, but figured I'd at least mention how things are going on this thread too. Thanks, Conor. 1 - https://lore.kernel.org/linux-riscv/20230419035646.43702-1-changhuang.liang@starfivetech.com/T/#m708770e9596098214df769bcc2bdaf9c1a46ca98 > + > +required: > + - compatible > + - reg > + > +additionalProperties: false > + > +examples: > + - | > + syscon@10240000 { > + compatible = "starfive,jh7110-stg-syscon", "syscon"; > + reg = <0x10240000 0x1000>; > + }; > + > + syscon@13030000 { > + compatible = "starfive,jh7110-sys-syscon", "syscon", "simple-mfd"; > + reg = <0x13030000 0x1000>; > + }; > + > +... > diff --git a/MAINTAINERS b/MAINTAINERS > index 03051ae2e9e5..0fafeea8ebdb 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -19917,6 +19917,11 @@ S: Supported > F: Documentation/devicetree/bindings/clock/starfive,jh7110-pll.yaml > F: drivers/clk/starfive/clk-starfive-jh7110-pll.* > > +STARFIVE JH7110 SYSCON > +M: William Qiu <william.qiu@starfivetech.com> > +S: Supported > +F: Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml > + > STARFIVE JH71X0 CLOCK DRIVERS > M: Emil Renner Berthing <kernel@esmil.dk> > M: Hal Feng <hal.feng@starfivetech.com> > @@ -19954,6 +19959,7 @@ STARFIVE SOC DRIVERS > M: Conor Dooley <conor@kernel.org> > S: Maintained > T: git https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/ > +F: Documentation/devicetree/bindings/soc/starfive/ > F: drivers/soc/starfive/ > > STARFIVE TRNG DRIVER > -- > 2.25.1 >
On Mon, Apr 24, 2023 at 06:15:47PM +0100, Conor Dooley wrote: > On Fri, Apr 14, 2023 at 10:41:55AM +0800, Xingyu Wu wrote: > > From: William Qiu <william.qiu@starfivetech.com> > > > > Add documentation to describe StarFive System Controller Registers. > > > > Signed-off-by: William Qiu <william.qiu@starfivetech.com> > > --- > > .../soc/starfive/starfive,jh7110-syscon.yaml | 58 +++++++++++++++++++ > > MAINTAINERS | 6 ++ > > 2 files changed, 64 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml > > > > diff --git a/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml > > new file mode 100644 > > index 000000000000..de086e74a229 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml > > @@ -0,0 +1,58 @@ > > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/soc/starfive/starfive,jh7110-syscon.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: StarFive JH7110 SoC system controller > > + > > +maintainers: > > + - William Qiu <william.qiu@starfivetech.com> > > + > > +description: | > > + The StarFive JH7110 SoC system controller provides register information such > > + as offset, mask and shift to configure related modules such as MMC and PCIe. > > + > > +properties: > > + compatible: > > + oneOf: > > + - items: > > + - enum: > > + - starfive,jh7110-aon-syscon > > + - starfive,jh7110-sys-syscon > > + - const: syscon > > + - const: simple-mfd > > + - items: > > + - const: starfive,jh7110-stg-syscon > > + - const: syscon > > + > > + reg: > > + maxItems: 1 > > + > > + clock-controller: > > + $ref: /schemas/clock/starfive,jh7110-pll.yaml# > > + type: object > > + > > + power-controller: > > + $ref: /schemas/power/starfive,jh7110-pmu.yaml# > > + type: object > > My plan was to grab this patch after the merge window, but there's been > some back and forth [1] about what exactly should be a power-controller > here. Given the merge window is open & I know Emil wants to look at the > various clock bits for the JH7110, I don't think there's a pressing need > for you to do anything here, but figured I'd at least mention how things > are going on this thread too. To follow up on this, it transpired in that thread that this node, not a child node, should be the power controller. Up to you StarFive folk how you wish to resend, but I am fine with it being in this series, I shall just not pick up the soc driver patches until the resent binding is applied by Stephen. Thanks, Conor.
On 2023/5/9 3:24, Conor Dooley wrote: > On Mon, Apr 24, 2023 at 06:15:47PM +0100, Conor Dooley wrote: >> On Fri, Apr 14, 2023 at 10:41:55AM +0800, Xingyu Wu wrote: >> > From: William Qiu <william.qiu@starfivetech.com> >> > >> > Add documentation to describe StarFive System Controller Registers. >> > >> > Signed-off-by: William Qiu <william.qiu@starfivetech.com> >> > --- >> > .../soc/starfive/starfive,jh7110-syscon.yaml | 58 +++++++++++++++++++ >> > MAINTAINERS | 6 ++ >> > 2 files changed, 64 insertions(+) >> > create mode 100644 Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml >> > >> > diff --git a/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml >> > new file mode 100644 >> > index 000000000000..de086e74a229 >> > --- /dev/null >> > +++ b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml >> > @@ -0,0 +1,58 @@ >> > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) >> > +%YAML 1.2 >> > +--- >> > +$id: http://devicetree.org/schemas/soc/starfive/starfive,jh7110-syscon.yaml# >> > +$schema: http://devicetree.org/meta-schemas/core.yaml# >> > + >> > +title: StarFive JH7110 SoC system controller >> > + >> > +maintainers: >> > + - William Qiu <william.qiu@starfivetech.com> >> > + >> > +description: | >> > + The StarFive JH7110 SoC system controller provides register information such >> > + as offset, mask and shift to configure related modules such as MMC and PCIe. >> > + >> > +properties: >> > + compatible: >> > + oneOf: >> > + - items: >> > + - enum: >> > + - starfive,jh7110-aon-syscon >> > + - starfive,jh7110-sys-syscon >> > + - const: syscon >> > + - const: simple-mfd >> > + - items: >> > + - const: starfive,jh7110-stg-syscon >> > + - const: syscon >> > + >> > + reg: >> > + maxItems: 1 >> > + >> > + clock-controller: >> > + $ref: /schemas/clock/starfive,jh7110-pll.yaml# >> > + type: object >> > + >> > + power-controller: >> > + $ref: /schemas/power/starfive,jh7110-pmu.yaml# >> > + type: object >> >> My plan was to grab this patch after the merge window, but there's been >> some back and forth [1] about what exactly should be a power-controller >> here. Given the merge window is open & I know Emil wants to look at the >> various clock bits for the JH7110, I don't think there's a pressing need >> for you to do anything here, but figured I'd at least mention how things >> are going on this thread too. > > To follow up on this, it transpired in that thread that this node, not a > child node, should be the power controller. > > Up to you StarFive folk how you wish to resend, but I am fine with it > being in this series, I shall just not pick up the soc driver patches > until the resent binding is applied by Stephen. > Thanks. I had discussed with changhuang.liang about this. And I will drop the 'starfive,jh7110-aon-syscon' and 'power-controller' in next patchset. Changhuang will take these in his patchset. Best regards, Xingyu Wu
On 9 May 2023 07:23:18 IST, Xingyu Wu <xingyu.wu@starfivetech.com> wrote: >On 2023/5/9 3:24, Conor Dooley wrote: >> On Mon, Apr 24, 2023 at 06:15:47PM +0100, Conor Dooley wrote: >>> On Fri, Apr 14, 2023 at 10:41:55AM +0800, Xingyu Wu wrote: >>> > From: William Qiu <william.qiu@starfivetech.com> >>> > >>> > Add documentation to describe StarFive System Controller Registers. >>> > >>> > Signed-off-by: William Qiu <william.qiu@starfivetech.com> >>> > --- >>> > .../soc/starfive/starfive,jh7110-syscon.yaml | 58 +++++++++++++++++++ >>> > MAINTAINERS | 6 ++ >>> > 2 files changed, 64 insertions(+) >>> > create mode 100644 Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml >>> > >>> > diff --git a/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml >>> > new file mode 100644 >>> > index 000000000000..de086e74a229 >>> > --- /dev/null >>> > +++ b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml >>> > @@ -0,0 +1,58 @@ >>> > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) >>> > +%YAML 1.2 >>> > +--- >>> > +$id: http://devicetree.org/schemas/soc/starfive/starfive,jh7110-syscon.yaml# >>> > +$schema: http://devicetree.org/meta-schemas/core.yaml# >>> > + >>> > +title: StarFive JH7110 SoC system controller >>> > + >>> > +maintainers: >>> > + - William Qiu <william.qiu@starfivetech.com> >>> > + >>> > +description: | >>> > + The StarFive JH7110 SoC system controller provides register information such >>> > + as offset, mask and shift to configure related modules such as MMC and PCIe. >>> > + >>> > +properties: >>> > + compatible: >>> > + oneOf: >>> > + - items: >>> > + - enum: >>> > + - starfive,jh7110-aon-syscon >>> > + - starfive,jh7110-sys-syscon >>> > + - const: syscon >>> > + - const: simple-mfd >>> > + - items: >>> > + - const: starfive,jh7110-stg-syscon >>> > + - const: syscon >>> > + >>> > + reg: >>> > + maxItems: 1 >>> > + >>> > + clock-controller: >>> > + $ref: /schemas/clock/starfive,jh7110-pll.yaml# >>> > + type: object >>> > + >>> > + power-controller: >>> > + $ref: /schemas/power/starfive,jh7110-pmu.yaml# >>> > + type: object >>> >>> My plan was to grab this patch after the merge window, but there's been >>> some back and forth [1] about what exactly should be a power-controller >>> here. Given the merge window is open & I know Emil wants to look at the >>> various clock bits for the JH7110, I don't think there's a pressing need >>> for you to do anything here, but figured I'd at least mention how things >>> are going on this thread too. >> >> To follow up on this, it transpired in that thread that this node, not a >> child node, should be the power controller. >> >> Up to you StarFive folk how you wish to resend, but I am fine with it >> being in this series, I shall just not pick up the soc driver patches >> until the resent binding is applied by Stephen. >> > >Thanks. I had discussed with changhuang.liang about this. And I will drop >the 'starfive,jh7110-aon-syscon' and 'power-controller' in next patchset. >Changhuang will take these in his patchset. Won't that result in broken bindings, since there's a ref to the pll binding? Keeping it in the same series (i.e. this one) makes the most sense to me. Cheers, Conor. > >Best regards, >Xingyu Wu >
On 2023/5/9 14:35, Conor Dooley wrote: > > > On 9 May 2023 07:23:18 IST, Xingyu Wu <xingyu.wu@starfivetech.com> wrote: >>On 2023/5/9 3:24, Conor Dooley wrote: >>> On Mon, Apr 24, 2023 at 06:15:47PM +0100, Conor Dooley wrote: >>>> On Fri, Apr 14, 2023 at 10:41:55AM +0800, Xingyu Wu wrote: >>>> > From: William Qiu <william.qiu@starfivetech.com> >>>> > >>>> > Add documentation to describe StarFive System Controller Registers. >>>> > >>>> > Signed-off-by: William Qiu <william.qiu@starfivetech.com> >>>> > --- >>>> > .../soc/starfive/starfive,jh7110-syscon.yaml | 58 +++++++++++++++++++ >>>> > MAINTAINERS | 6 ++ >>>> > 2 files changed, 64 insertions(+) >>>> > create mode 100644 Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml >>>> > >>>> > diff --git a/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml >>>> > new file mode 100644 >>>> > index 000000000000..de086e74a229 >>>> > --- /dev/null >>>> > +++ b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml >>>> > @@ -0,0 +1,58 @@ >>>> > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) >>>> > +%YAML 1.2 >>>> > +--- >>>> > +$id: http://devicetree.org/schemas/soc/starfive/starfive,jh7110-syscon.yaml# >>>> > +$schema: http://devicetree.org/meta-schemas/core.yaml# >>>> > + >>>> > +title: StarFive JH7110 SoC system controller >>>> > + >>>> > +maintainers: >>>> > + - William Qiu <william.qiu@starfivetech.com> >>>> > + >>>> > +description: | >>>> > + The StarFive JH7110 SoC system controller provides register information such >>>> > + as offset, mask and shift to configure related modules such as MMC and PCIe. >>>> > + >>>> > +properties: >>>> > + compatible: >>>> > + oneOf: >>>> > + - items: >>>> > + - enum: >>>> > + - starfive,jh7110-aon-syscon >>>> > + - starfive,jh7110-sys-syscon >>>> > + - const: syscon >>>> > + - const: simple-mfd >>>> > + - items: >>>> > + - const: starfive,jh7110-stg-syscon >>>> > + - const: syscon >>>> > + >>>> > + reg: >>>> > + maxItems: 1 >>>> > + >>>> > + clock-controller: >>>> > + $ref: /schemas/clock/starfive,jh7110-pll.yaml# >>>> > + type: object >>>> > + >>>> > + power-controller: >>>> > + $ref: /schemas/power/starfive,jh7110-pmu.yaml# >>>> > + type: object >>>> >>>> My plan was to grab this patch after the merge window, but there's been >>>> some back and forth [1] about what exactly should be a power-controller >>>> here. Given the merge window is open & I know Emil wants to look at the >>>> various clock bits for the JH7110, I don't think there's a pressing need >>>> for you to do anything here, but figured I'd at least mention how things >>>> are going on this thread too. >>> >>> To follow up on this, it transpired in that thread that this node, not a >>> child node, should be the power controller. >>> >>> Up to you StarFive folk how you wish to resend, but I am fine with it >>> being in this series, I shall just not pick up the soc driver patches >>> until the resent binding is applied by Stephen. >>> >> >>Thanks. I had discussed with changhuang.liang about this. And I will drop >>the 'starfive,jh7110-aon-syscon' and 'power-controller' in next patchset. >>Changhuang will take these in his patchset. > > Won't that result in broken bindings, since there's a ref to the pll binding? > Keeping it in the same series (i.e. this one) makes > the most sense to me. > I will keep the 'sys-syscon' and 'stg-syscon'. The ref just follows the 'sys-syscon' so I also keep it and the pll binding. I also hope to add the 'aon-syscon' in this same series but it should be the power controller, so I have to give up it. Best regards, Xingyu Wu
On 2023/5/9 14:52, Xingyu Wu wrote: > On 2023/5/9 14:35, Conor Dooley wrote: >> >> >> On 9 May 2023 07:23:18 IST, Xingyu Wu <xingyu.wu@starfivetech.com> wrote: >>>On 2023/5/9 3:24, Conor Dooley wrote: >>>> On Mon, Apr 24, 2023 at 06:15:47PM +0100, Conor Dooley wrote: >>>>> On Fri, Apr 14, 2023 at 10:41:55AM +0800, Xingyu Wu wrote: >>>>> > From: William Qiu <william.qiu@starfivetech.com> >>>>> > >>>>> > Add documentation to describe StarFive System Controller Registers. >>>>> > >>>>> > Signed-off-by: William Qiu <william.qiu@starfivetech.com> >>>>> > --- >>>>> > .../soc/starfive/starfive,jh7110-syscon.yaml | 58 +++++++++++++++++++ >>>>> > MAINTAINERS | 6 ++ >>>>> > 2 files changed, 64 insertions(+) >>>>> > create mode 100644 Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml >>>>> > >>>>> > diff --git a/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml >>>>> > new file mode 100644 >>>>> > index 000000000000..de086e74a229 >>>>> > --- /dev/null >>>>> > +++ b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml >>>>> > @@ -0,0 +1,58 @@ >>>>> > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) >>>>> > +%YAML 1.2 >>>>> > +--- >>>>> > +$id: http://devicetree.org/schemas/soc/starfive/starfive,jh7110-syscon.yaml# >>>>> > +$schema: http://devicetree.org/meta-schemas/core.yaml# >>>>> > + >>>>> > +title: StarFive JH7110 SoC system controller >>>>> > + >>>>> > +maintainers: >>>>> > + - William Qiu <william.qiu@starfivetech.com> >>>>> > + >>>>> > +description: | >>>>> > + The StarFive JH7110 SoC system controller provides register information such >>>>> > + as offset, mask and shift to configure related modules such as MMC and PCIe. >>>>> > + >>>>> > +properties: >>>>> > + compatible: >>>>> > + oneOf: >>>>> > + - items: >>>>> > + - enum: >>>>> > + - starfive,jh7110-aon-syscon >>>>> > + - starfive,jh7110-sys-syscon >>>>> > + - const: syscon >>>>> > + - const: simple-mfd >>>>> > + - items: >>>>> > + - const: starfive,jh7110-stg-syscon >>>>> > + - const: syscon >>>>> > + >>>>> > + reg: >>>>> > + maxItems: 1 >>>>> > + >>>>> > + clock-controller: >>>>> > + $ref: /schemas/clock/starfive,jh7110-pll.yaml# >>>>> > + type: object >>>>> > + >>>>> > + power-controller: >>>>> > + $ref: /schemas/power/starfive,jh7110-pmu.yaml# >>>>> > + type: object >>>>> >>>>> My plan was to grab this patch after the merge window, but there's been >>>>> some back and forth [1] about what exactly should be a power-controller >>>>> here. Given the merge window is open & I know Emil wants to look at the >>>>> various clock bits for the JH7110, I don't think there's a pressing need >>>>> for you to do anything here, but figured I'd at least mention how things >>>>> are going on this thread too. >>>> >>>> To follow up on this, it transpired in that thread that this node, not a >>>> child node, should be the power controller. >>>> >>>> Up to you StarFive folk how you wish to resend, but I am fine with it >>>> being in this series, I shall just not pick up the soc driver patches >>>> until the resent binding is applied by Stephen. >>>> >>> >>>Thanks. I had discussed with changhuang.liang about this. And I will drop >>>the 'starfive,jh7110-aon-syscon' and 'power-controller' in next patchset. >>>Changhuang will take these in his patchset. >> >> Won't that result in broken bindings, since there's a ref to the pll binding? >> Keeping it in the same series (i.e. this one) makes >> the most sense to me. >> > > I will keep the 'sys-syscon' and 'stg-syscon'. The ref just follows the 'sys-syscon' > so I also keep it and the pll binding. > I also hope to add the 'aon-syscon' in this same series but it should be the power > controller, so I have to give up it. > I synchronized with Chang Huang. It is decided to keep 'aon-syscon' as the power controller in this and do not add child node in 'aon-syscon'. And I will update it in the next version of patch. Best regards, Xingyu Wu
diff --git a/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml new file mode 100644 index 000000000000..de086e74a229 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/starfive/starfive,jh7110-syscon.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH7110 SoC system controller + +maintainers: + - William Qiu <william.qiu@starfivetech.com> + +description: | + The StarFive JH7110 SoC system controller provides register information such + as offset, mask and shift to configure related modules such as MMC and PCIe. + +properties: + compatible: + oneOf: + - items: + - enum: + - starfive,jh7110-aon-syscon + - starfive,jh7110-sys-syscon + - const: syscon + - const: simple-mfd + - items: + - const: starfive,jh7110-stg-syscon + - const: syscon + + reg: + maxItems: 1 + + clock-controller: + $ref: /schemas/clock/starfive,jh7110-pll.yaml# + type: object + + power-controller: + $ref: /schemas/power/starfive,jh7110-pmu.yaml# + type: object + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + syscon@10240000 { + compatible = "starfive,jh7110-stg-syscon", "syscon"; + reg = <0x10240000 0x1000>; + }; + + syscon@13030000 { + compatible = "starfive,jh7110-sys-syscon", "syscon", "simple-mfd"; + reg = <0x13030000 0x1000>; + }; + +... diff --git a/MAINTAINERS b/MAINTAINERS index 03051ae2e9e5..0fafeea8ebdb 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -19917,6 +19917,11 @@ S: Supported F: Documentation/devicetree/bindings/clock/starfive,jh7110-pll.yaml F: drivers/clk/starfive/clk-starfive-jh7110-pll.* +STARFIVE JH7110 SYSCON +M: William Qiu <william.qiu@starfivetech.com> +S: Supported +F: Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml + STARFIVE JH71X0 CLOCK DRIVERS M: Emil Renner Berthing <kernel@esmil.dk> M: Hal Feng <hal.feng@starfivetech.com> @@ -19954,6 +19959,7 @@ STARFIVE SOC DRIVERS M: Conor Dooley <conor@kernel.org> S: Maintained T: git https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/ +F: Documentation/devicetree/bindings/soc/starfive/ F: drivers/soc/starfive/ STARFIVE TRNG DRIVER