| Message ID | 20230414120520.360291-5-joychakr@google.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | spi: dw: DW SPI DMA Driver updates | expand |
On Fri, Apr 14, 2023 at 12:05:19PM +0000, Joy Chakraborty wrote: > Store address width capabilities of DMA controller during init and check > the same per transfer to make sure the bits/word requirement can be met. > > Current DW DMA driver requires both tx and rx channel to be configured > and functional hence a subset of both tx and rx channel address width > capability is checked with the width requirement(n_bytes) for a > transfer. ... > + /* > + * Assuming both channels belong to the same DMA controller hence the > + * address width capabilities most likely would be the same. I would add something to explain the side of these address width, like * Assuming both channels belong to the same DMA controller hence * the peripheral side address width capabilities most likely would * be the same. > + */
diff --git a/drivers/spi/spi-dw-dma.c b/drivers/spi/spi-dw-dma.c index e1dd13fe4fd0..45980c46946d 100644 --- a/drivers/spi/spi-dw-dma.c +++ b/drivers/spi/spi-dw-dma.c @@ -97,6 +97,14 @@ static int dw_spi_dma_caps_init(struct dw_spi *dws) dws->dma_sg_burst = rx.max_sg_burst; else dws->dma_sg_burst = 0; + + /* + * Assuming both channels belong to the same DMA controller hence the + * address width capabilities most likely would be the same. + */ + dws->dma_addr_widths = tx.dst_addr_widths & rx.src_addr_widths; + + return 0; } static int dw_spi_dma_init_mfld(struct device *dev, struct dw_spi *dws) @@ -237,10 +245,15 @@ static bool dw_spi_can_dma(struct spi_controller *master, struct spi_device *spi, struct spi_transfer *xfer) { struct dw_spi *dws = spi_controller_get_devdata(master); + enum dma_slave_buswidth dma_bus_width; - return xfer->len > dws->fifo_len; -} + if (xfer->len <= dws->fifo_len) + return false; + dma_bus_width = dw_spi_dma_convert_width(dws->n_bytes); + + return dws->dma_addr_widths & BIT(dma_bus_width); +} static int dw_spi_dma_wait(struct dw_spi *dws, unsigned int len, u32 speed) { diff --git a/drivers/spi/spi-dw.h b/drivers/spi/spi-dw.h index 9e8eb2b52d5c..3962e6dcf880 100644 --- a/drivers/spi/spi-dw.h +++ b/drivers/spi/spi-dw.h @@ -190,6 +190,7 @@ struct dw_spi { struct dma_chan *rxchan; u32 rxburst; u32 dma_sg_burst; + u32 dma_addr_widths; unsigned long dma_chan_busy; dma_addr_t dma_addr; /* phy address of the Data register */ const struct dw_spi_dma_ops *dma_ops;
Store address width capabilities of DMA controller during init and check the same per transfer to make sure the bits/word requirement can be met. Current DW DMA driver requires both tx and rx channel to be configured and functional hence a subset of both tx and rx channel address width capability is checked with the width requirement(n_bytes) for a transfer. Signed-off-by: Joy Chakraborty <joychakr@google.com> --- drivers/spi/spi-dw-dma.c | 17 +++++++++++++++-- drivers/spi/spi-dw.h | 1 + 2 files changed, 16 insertions(+), 2 deletions(-)