diff mbox series

[1/8] drm/i915/mtl: Set has_llc=0

Message ID 20230419211219.2574008-2-fei.yang@intel.com (mailing list archive)
State New, archived
Headers show
Series drm/i915/mtl: Define MOCS and PAT tables for MTL | expand

Commit Message

Yang, Fei April 19, 2023, 9:12 p.m. UTC 
From: Fei Yang <fei.yang@intel.com>

On MTL, LLC is not shared between GT and CPU, set has_llc=0.

Signed-off-by: Fei Yang <fei.yang@intel.com>
---
 drivers/gpu/drm/i915/i915_pci.c | 1 +
 1 file changed, 1 insertion(+)

Comments

Andi Shyti April 19, 2023, 9:56 p.m. UTC | #1 
Hi Fei,

On Wed, Apr 19, 2023 at 02:12:12PM -0700, fei.yang@intel.com wrote:
> From: Fei Yang <fei.yang@intel.com>
> 
> On MTL, LLC is not shared between GT and CPU, set has_llc=0.
> 
> Signed-off-by: Fei Yang <fei.yang@intel.com>

just an unanswered questino from Nirmoy:

This statement is bit unclear to me.  I would say "On MTL, LLC
is not shared between GT and CPU"

Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>
Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com>
Reviewed-by: Nirmoy Das <nirmoy.das@intel.com>

Andi
Yang, Fei April 19, 2023, 10:10 p.m. UTC | #2 
> Hi Fei,
>
> On Wed, Apr 19, 2023 at 02:12:12PM -0700, fei.yang@intel.com wrote:
>> From: Fei Yang <fei.yang@intel.com>
>>
>> On MTL, LLC is not shared between GT and CPU, set has_llc=0.
>>
>> Signed-off-by: Fei Yang <fei.yang@intel.com>
>
> just an unanswered questino from Nirmoy:
>
> This statement is bit unclear to me.  I would say "On MTL, LLC is not shared between GT and CPU"

I have updated the commit message accordingly in this version. see above.

> Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>
> Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com>
> Reviewed-by: Nirmoy Das <nirmoy.das@intel.com>
>
> Andi
Andi Shyti April 19, 2023, 10:11 p.m. UTC | #3 
Hi Fei,

On Wed, Apr 19, 2023 at 10:10:24PM +0000, Yang, Fei wrote:
> > Hi Fei,
> >
> > On Wed, Apr 19, 2023 at 02:12:12PM -0700, fei.yang@intel.com wrote:
> >> From: Fei Yang <fei.yang@intel.com>
> >>
> >> On MTL, LLC is not shared between GT and CPU, set has_llc=0.
> >>
> >> Signed-off-by: Fei Yang <fei.yang@intel.com>
> >
> > just an unanswered questino from Nirmoy:
> >
> > This statement is bit unclear to me.  I would say "On MTL, LLC is not shared between GT and CPU"
> 
> I have updated the commit message accordingly in this version. see above.

oh... sorry... I got confused... never mind! :)

Thanks!
Andi

> > Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>
> > Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com>
> > Reviewed-by: Nirmoy Das <nirmoy.das@intel.com>
> >
> > Andi
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index d64e074d7457..272a8ba37b64 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -1147,6 +1147,7 @@  static const struct intel_device_info mtl_info = {
 	.has_flat_ccs = 0,
 	.has_gmd_id = 1,
 	.has_guc_deprivilege = 1,
+	.has_llc = 0,
 	.has_mslice_steering = 0,
 	.has_snoop = 1,
 	.__runtime.memory_regions = REGION_SMEM | REGION_STOLEN_LMEM,