| Message ID | 1682725511-18185-5-git-send-email-quic_khsieh@quicinc.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | add DSC 1.2 dpu supports | expand |
On 29/04/2023 02:45, Kuogee Hsieh wrote: > From: Abhinav Kumar <quic_abhinavk@quicinc.com> > > In preparation of calling ping-pong DSC related functions only > for chipsets which have such a design add the dsc blocks for the > chipsets for which DSC is present but was not added in the catalog. Why/how is it prearing us for such calling? The change itself LGTM. > > Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> > --- > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 7 +++++++ > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 11 +++++++++++ > 2 files changed, 18 insertions(+) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h > index 2b3ae84..17f821c 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h > @@ -126,6 +126,11 @@ static const struct dpu_pingpong_cfg msm8998_pp[] = { > DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15)), > }; > > +static const struct dpu_dsc_cfg msm8998_dsc[] = { > + DSC_BLK("dsc_0", DSC_0, 0x80000, 0), > + DSC_BLK("dsc_1", DSC_1, 0x80400, 0), > +}; > + > static const struct dpu_dspp_cfg msm8998_dspp[] = { > DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_MSM8998_MASK, > &msm8998_dspp_sblk), > @@ -191,6 +196,8 @@ const struct dpu_mdss_cfg dpu_msm8998_cfg = { > .dspp = msm8998_dspp, > .pingpong_count = ARRAY_SIZE(msm8998_pp), > .pingpong = msm8998_pp, > + .dsc_count = ARRAY_SIZE(msm8998_dsc), > + .dsc = msm8998_dsc, > .intf_count = ARRAY_SIZE(msm8998_intf), > .intf = msm8998_intf, > .vbif_count = ARRAY_SIZE(msm8998_vbif), > diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h > index e3bdfe7..5bb9882 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h > @@ -142,6 +142,15 @@ static const struct dpu_merge_3d_cfg sc8180x_merge_3d[] = { > MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x83200), > }; > > +static const struct dpu_dsc_cfg sc8180x_dsc[] = { > + DSC_BLK("dsc_0", DSC_0, 0x80000, BIT(DPU_DSC_OUTPUT_CTRL)), > + DSC_BLK("dsc_1", DSC_1, 0x80400, BIT(DPU_DSC_OUTPUT_CTRL)), > + DSC_BLK("dsc_2", DSC_2, 0x80800, BIT(DPU_DSC_OUTPUT_CTRL)), > + DSC_BLK("dsc_3", DSC_3, 0x80c00, BIT(DPU_DSC_OUTPUT_CTRL)), > + DSC_BLK("dsc_4", DSC_4, 0x81000, BIT(DPU_DSC_OUTPUT_CTRL)), > + DSC_BLK("dsc_5", DSC_5, 0x81400, BIT(DPU_DSC_OUTPUT_CTRL)), > +}; > + > static const struct dpu_intf_cfg sc8180x_intf[] = { > INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 24, 25), > INTF_BLK("intf_1", INTF_1, 0x6a800, 0x2bc, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27), > @@ -192,6 +201,8 @@ const struct dpu_mdss_cfg dpu_sc8180x_cfg = { > .mixer = sc8180x_lm, > .pingpong_count = ARRAY_SIZE(sc8180x_pp), > .pingpong = sc8180x_pp, > + .dsc_count = ARRAY_SIZE(sc8180x_dsc), > + .dsc = sc8180x_dsc, > .merge_3d_count = ARRAY_SIZE(sc8180x_merge_3d), > .merge_3d = sc8180x_merge_3d, > .intf_count = ARRAY_SIZE(sc8180x_intf),
On 4/28/2023 5:35 PM, Dmitry Baryshkov wrote: > On 29/04/2023 02:45, Kuogee Hsieh wrote: >> From: Abhinav Kumar <quic_abhinavk@quicinc.com> >> >> In preparation of calling ping-pong DSC related functions only >> for chipsets which have such a design add the dsc blocks for the >> chipsets for which DSC is present but was not added in the catalog. > > Why/how is it prearing us for such calling? > > The change itself LGTM. The next change adds DPU_PINGPONG_DSC feature flag to chipsets where it is supported. But when I checked there were many chipsets where DSC is present but were not added in catalog. Without doing that, the next change was originally adding 0 to the feature flags of those chipsets which didnt seem right to me. This seemed like the right way to do it to first add the DSC blocks for those chipsets and add the feature flag to them in the next change. > >> >> Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> >> --- >> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 7 +++++++ >> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 11 >> +++++++++++ >> 2 files changed, 18 insertions(+) >> >> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h >> b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h >> index 2b3ae84..17f821c 100644 >> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h >> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h >> @@ -126,6 +126,11 @@ static const struct dpu_pingpong_cfg msm8998_pp[] >> = { >> DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15)), >> }; >> +static const struct dpu_dsc_cfg msm8998_dsc[] = { >> + DSC_BLK("dsc_0", DSC_0, 0x80000, 0), >> + DSC_BLK("dsc_1", DSC_1, 0x80400, 0), >> +}; >> + >> static const struct dpu_dspp_cfg msm8998_dspp[] = { >> DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_MSM8998_MASK, >> &msm8998_dspp_sblk), >> @@ -191,6 +196,8 @@ const struct dpu_mdss_cfg dpu_msm8998_cfg = { >> .dspp = msm8998_dspp, >> .pingpong_count = ARRAY_SIZE(msm8998_pp), >> .pingpong = msm8998_pp, >> + .dsc_count = ARRAY_SIZE(msm8998_dsc), >> + .dsc = msm8998_dsc, >> .intf_count = ARRAY_SIZE(msm8998_intf), >> .intf = msm8998_intf, >> .vbif_count = ARRAY_SIZE(msm8998_vbif), >> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h >> b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h >> index e3bdfe7..5bb9882 100644 >> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h >> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h >> @@ -142,6 +142,15 @@ static const struct dpu_merge_3d_cfg >> sc8180x_merge_3d[] = { >> MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x83200), >> }; >> +static const struct dpu_dsc_cfg sc8180x_dsc[] = { >> + DSC_BLK("dsc_0", DSC_0, 0x80000, BIT(DPU_DSC_OUTPUT_CTRL)), >> + DSC_BLK("dsc_1", DSC_1, 0x80400, BIT(DPU_DSC_OUTPUT_CTRL)), >> + DSC_BLK("dsc_2", DSC_2, 0x80800, BIT(DPU_DSC_OUTPUT_CTRL)), >> + DSC_BLK("dsc_3", DSC_3, 0x80c00, BIT(DPU_DSC_OUTPUT_CTRL)), >> + DSC_BLK("dsc_4", DSC_4, 0x81000, BIT(DPU_DSC_OUTPUT_CTRL)), >> + DSC_BLK("dsc_5", DSC_5, 0x81400, BIT(DPU_DSC_OUTPUT_CTRL)), >> +}; >> + >> static const struct dpu_intf_cfg sc8180x_intf[] = { >> INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, >> MSM_DP_CONTROLLER_0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 24, 25), >> INTF_BLK("intf_1", INTF_1, 0x6a800, 0x2bc, INTF_DSI, 0, 24, >> INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27), >> @@ -192,6 +201,8 @@ const struct dpu_mdss_cfg dpu_sc8180x_cfg = { >> .mixer = sc8180x_lm, >> .pingpong_count = ARRAY_SIZE(sc8180x_pp), >> .pingpong = sc8180x_pp, >> + .dsc_count = ARRAY_SIZE(sc8180x_dsc), >> + .dsc = sc8180x_dsc, >> .merge_3d_count = ARRAY_SIZE(sc8180x_merge_3d), >> .merge_3d = sc8180x_merge_3d, >> .intf_count = ARRAY_SIZE(sc8180x_intf), >
On 29/04/2023 04:03, Abhinav Kumar wrote: > > > On 4/28/2023 5:35 PM, Dmitry Baryshkov wrote: >> On 29/04/2023 02:45, Kuogee Hsieh wrote: >>> From: Abhinav Kumar <quic_abhinavk@quicinc.com> >>> >>> In preparation of calling ping-pong DSC related functions only >>> for chipsets which have such a design add the dsc blocks for the >>> chipsets for which DSC is present but was not added in the catalog. >> >> Why/how is it prearing us for such calling? >> >> The change itself LGTM. > > The next change adds DPU_PINGPONG_DSC feature flag to chipsets where it > is supported. But when I checked there were many chipsets where DSC is > present but were not added in catalog. > > Without doing that, the next change was originally adding 0 to the > feature flags of those chipsets which didnt seem right to me. > > This seemed like the right way to do it to first add the DSC blocks for > those chipsets and add the feature flag to them in the next change. I'd write something like 'for completeness, add DSC blocks for platforms which missed them'. > >> >>> >>> Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> >>> --- >>> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 7 +++++++ >>> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 11 >>> +++++++++++ >>> 2 files changed, 18 insertions(+) >>> >>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h >>> b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h >>> index 2b3ae84..17f821c 100644 >>> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h >>> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h >>> @@ -126,6 +126,11 @@ static const struct dpu_pingpong_cfg >>> msm8998_pp[] = { >>> DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15)), >>> }; >>> +static const struct dpu_dsc_cfg msm8998_dsc[] = { >>> + DSC_BLK("dsc_0", DSC_0, 0x80000, 0), >>> + DSC_BLK("dsc_1", DSC_1, 0x80400, 0), >>> +}; >>> + >>> static const struct dpu_dspp_cfg msm8998_dspp[] = { >>> DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_MSM8998_MASK, >>> &msm8998_dspp_sblk), >>> @@ -191,6 +196,8 @@ const struct dpu_mdss_cfg dpu_msm8998_cfg = { >>> .dspp = msm8998_dspp, >>> .pingpong_count = ARRAY_SIZE(msm8998_pp), >>> .pingpong = msm8998_pp, >>> + .dsc_count = ARRAY_SIZE(msm8998_dsc), >>> + .dsc = msm8998_dsc, >>> .intf_count = ARRAY_SIZE(msm8998_intf), >>> .intf = msm8998_intf, >>> .vbif_count = ARRAY_SIZE(msm8998_vbif), >>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h >>> b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h >>> index e3bdfe7..5bb9882 100644 >>> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h >>> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h >>> @@ -142,6 +142,15 @@ static const struct dpu_merge_3d_cfg >>> sc8180x_merge_3d[] = { >>> MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x83200), >>> }; >>> +static const struct dpu_dsc_cfg sc8180x_dsc[] = { >>> + DSC_BLK("dsc_0", DSC_0, 0x80000, BIT(DPU_DSC_OUTPUT_CTRL)), >>> + DSC_BLK("dsc_1", DSC_1, 0x80400, BIT(DPU_DSC_OUTPUT_CTRL)), >>> + DSC_BLK("dsc_2", DSC_2, 0x80800, BIT(DPU_DSC_OUTPUT_CTRL)), >>> + DSC_BLK("dsc_3", DSC_3, 0x80c00, BIT(DPU_DSC_OUTPUT_CTRL)), >>> + DSC_BLK("dsc_4", DSC_4, 0x81000, BIT(DPU_DSC_OUTPUT_CTRL)), >>> + DSC_BLK("dsc_5", DSC_5, 0x81400, BIT(DPU_DSC_OUTPUT_CTRL)), >>> +}; >>> + >>> static const struct dpu_intf_cfg sc8180x_intf[] = { >>> INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, >>> MSM_DP_CONTROLLER_0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 24, 25), >>> INTF_BLK("intf_1", INTF_1, 0x6a800, 0x2bc, INTF_DSI, 0, 24, >>> INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27), >>> @@ -192,6 +201,8 @@ const struct dpu_mdss_cfg dpu_sc8180x_cfg = { >>> .mixer = sc8180x_lm, >>> .pingpong_count = ARRAY_SIZE(sc8180x_pp), >>> .pingpong = sc8180x_pp, >>> + .dsc_count = ARRAY_SIZE(sc8180x_dsc), >>> + .dsc = sc8180x_dsc, >>> .merge_3d_count = ARRAY_SIZE(sc8180x_merge_3d), >>> .merge_3d = sc8180x_merge_3d, >>> .intf_count = ARRAY_SIZE(sc8180x_intf), >>
On 4/28/2023 6:04 PM, Dmitry Baryshkov wrote: > On 29/04/2023 04:03, Abhinav Kumar wrote: >> >> >> On 4/28/2023 5:35 PM, Dmitry Baryshkov wrote: >>> On 29/04/2023 02:45, Kuogee Hsieh wrote: >>>> From: Abhinav Kumar <quic_abhinavk@quicinc.com> >>>> >>>> In preparation of calling ping-pong DSC related functions only >>>> for chipsets which have such a design add the dsc blocks for the >>>> chipsets for which DSC is present but was not added in the catalog. >>> >>> Why/how is it prearing us for such calling? >>> >>> The change itself LGTM. >> >> The next change adds DPU_PINGPONG_DSC feature flag to chipsets where >> it is supported. But when I checked there were many chipsets where DSC >> is present but were not added in catalog. >> >> Without doing that, the next change was originally adding 0 to the >> feature flags of those chipsets which didnt seem right to me. >> >> This seemed like the right way to do it to first add the DSC blocks >> for those chipsets and add the feature flag to them in the next change. > > I'd write something like 'for completeness, add DSC blocks for platforms > which missed them'. > Sure, ack. >> >>> >>>> >>>> Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> >>>> --- >>>> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 7 +++++++ >>>> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 11 >>>> +++++++++++ >>>> 2 files changed, 18 insertions(+) >>>> >>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h >>>> b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h >>>> index 2b3ae84..17f821c 100644 >>>> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h >>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h >>>> @@ -126,6 +126,11 @@ static const struct dpu_pingpong_cfg >>>> msm8998_pp[] = { >>>> DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15)), >>>> }; >>>> +static const struct dpu_dsc_cfg msm8998_dsc[] = { >>>> + DSC_BLK("dsc_0", DSC_0, 0x80000, 0), >>>> + DSC_BLK("dsc_1", DSC_1, 0x80400, 0), >>>> +}; >>>> + >>>> static const struct dpu_dspp_cfg msm8998_dspp[] = { >>>> DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_MSM8998_MASK, >>>> &msm8998_dspp_sblk), >>>> @@ -191,6 +196,8 @@ const struct dpu_mdss_cfg dpu_msm8998_cfg = { >>>> .dspp = msm8998_dspp, >>>> .pingpong_count = ARRAY_SIZE(msm8998_pp), >>>> .pingpong = msm8998_pp, >>>> + .dsc_count = ARRAY_SIZE(msm8998_dsc), >>>> + .dsc = msm8998_dsc, >>>> .intf_count = ARRAY_SIZE(msm8998_intf), >>>> .intf = msm8998_intf, >>>> .vbif_count = ARRAY_SIZE(msm8998_vbif), >>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h >>>> b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h >>>> index e3bdfe7..5bb9882 100644 >>>> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h >>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h >>>> @@ -142,6 +142,15 @@ static const struct dpu_merge_3d_cfg >>>> sc8180x_merge_3d[] = { >>>> MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x83200), >>>> }; >>>> +static const struct dpu_dsc_cfg sc8180x_dsc[] = { >>>> + DSC_BLK("dsc_0", DSC_0, 0x80000, BIT(DPU_DSC_OUTPUT_CTRL)), >>>> + DSC_BLK("dsc_1", DSC_1, 0x80400, BIT(DPU_DSC_OUTPUT_CTRL)), >>>> + DSC_BLK("dsc_2", DSC_2, 0x80800, BIT(DPU_DSC_OUTPUT_CTRL)), >>>> + DSC_BLK("dsc_3", DSC_3, 0x80c00, BIT(DPU_DSC_OUTPUT_CTRL)), >>>> + DSC_BLK("dsc_4", DSC_4, 0x81000, BIT(DPU_DSC_OUTPUT_CTRL)), >>>> + DSC_BLK("dsc_5", DSC_5, 0x81400, BIT(DPU_DSC_OUTPUT_CTRL)), >>>> +}; >>>> + >>>> static const struct dpu_intf_cfg sc8180x_intf[] = { >>>> INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, >>>> MSM_DP_CONTROLLER_0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 24, 25), >>>> INTF_BLK("intf_1", INTF_1, 0x6a800, 0x2bc, INTF_DSI, 0, 24, >>>> INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27), >>>> @@ -192,6 +201,8 @@ const struct dpu_mdss_cfg dpu_sc8180x_cfg = { >>>> .mixer = sc8180x_lm, >>>> .pingpong_count = ARRAY_SIZE(sc8180x_pp), >>>> .pingpong = sc8180x_pp, >>>> + .dsc_count = ARRAY_SIZE(sc8180x_dsc), >>>> + .dsc = sc8180x_dsc, >>>> .merge_3d_count = ARRAY_SIZE(sc8180x_merge_3d), >>>> .merge_3d = sc8180x_merge_3d, >>>> .intf_count = ARRAY_SIZE(sc8180x_intf), >>> >
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h index 2b3ae84..17f821c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h @@ -126,6 +126,11 @@ static const struct dpu_pingpong_cfg msm8998_pp[] = { DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15)), }; +static const struct dpu_dsc_cfg msm8998_dsc[] = { + DSC_BLK("dsc_0", DSC_0, 0x80000, 0), + DSC_BLK("dsc_1", DSC_1, 0x80400, 0), +}; + static const struct dpu_dspp_cfg msm8998_dspp[] = { DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_MSM8998_MASK, &msm8998_dspp_sblk), @@ -191,6 +196,8 @@ const struct dpu_mdss_cfg dpu_msm8998_cfg = { .dspp = msm8998_dspp, .pingpong_count = ARRAY_SIZE(msm8998_pp), .pingpong = msm8998_pp, + .dsc_count = ARRAY_SIZE(msm8998_dsc), + .dsc = msm8998_dsc, .intf_count = ARRAY_SIZE(msm8998_intf), .intf = msm8998_intf, .vbif_count = ARRAY_SIZE(msm8998_vbif), diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h index e3bdfe7..5bb9882 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h @@ -142,6 +142,15 @@ static const struct dpu_merge_3d_cfg sc8180x_merge_3d[] = { MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x83200), }; +static const struct dpu_dsc_cfg sc8180x_dsc[] = { + DSC_BLK("dsc_0", DSC_0, 0x80000, BIT(DPU_DSC_OUTPUT_CTRL)), + DSC_BLK("dsc_1", DSC_1, 0x80400, BIT(DPU_DSC_OUTPUT_CTRL)), + DSC_BLK("dsc_2", DSC_2, 0x80800, BIT(DPU_DSC_OUTPUT_CTRL)), + DSC_BLK("dsc_3", DSC_3, 0x80c00, BIT(DPU_DSC_OUTPUT_CTRL)), + DSC_BLK("dsc_4", DSC_4, 0x81000, BIT(DPU_DSC_OUTPUT_CTRL)), + DSC_BLK("dsc_5", DSC_5, 0x81400, BIT(DPU_DSC_OUTPUT_CTRL)), +}; + static const struct dpu_intf_cfg sc8180x_intf[] = { INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 24, 25), INTF_BLK("intf_1", INTF_1, 0x6a800, 0x2bc, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27), @@ -192,6 +201,8 @@ const struct dpu_mdss_cfg dpu_sc8180x_cfg = { .mixer = sc8180x_lm, .pingpong_count = ARRAY_SIZE(sc8180x_pp), .pingpong = sc8180x_pp, + .dsc_count = ARRAY_SIZE(sc8180x_dsc), + .dsc = sc8180x_dsc, .merge_3d_count = ARRAY_SIZE(sc8180x_merge_3d), .merge_3d = sc8180x_merge_3d, .intf_count = ARRAY_SIZE(sc8180x_intf),