| Message ID | 1682725511-18185-7-git-send-email-quic_khsieh@quicinc.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | add DSC 1.2 dpu supports | expand |
On 29/04/2023 02:45, Kuogee Hsieh wrote: > At current implementation, topology configuration is thrown away after > dpu_rm_reserve(). This patch save the topology so that it can be used > for DSC related calculation later. Even if we delay the virtual wide planes patchset, please don't save the topology in the encoder. If we get cloned encoders support (e.g. for CWB), the end topology will contain both WB and INTF entries and as such it will not be useable by a single encoder. Thus this change is not future-proof. > > Signed-off-by: Kuogee Hsieh <quic_khsieh@quicinc.com> > --- > drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 32 ++++++++++++++--------------- > 1 file changed, 16 insertions(+), 16 deletions(-) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c > index ecb87bc..2fdacf1 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c > @@ -542,13 +542,13 @@ bool dpu_encoder_use_dsc_merge(struct drm_encoder *drm_enc) > return (num_dsc > 0) && (num_dsc > intf_count); > } > > -static struct msm_display_topology dpu_encoder_get_topology( > +static void dpu_encoder_get_topology( > struct dpu_encoder_virt *dpu_enc, > struct dpu_kms *dpu_kms, > struct drm_display_mode *mode, > - struct drm_crtc_state *crtc_state) > + struct drm_crtc_state *crtc_state, > + struct msm_display_topology *topology) > { > - struct msm_display_topology topology = {0}; > int i, intf_count = 0; > > for (i = 0; i < MAX_PHYS_ENCODERS_PER_VIRTUAL; i++) > @@ -567,16 +567,16 @@ static struct msm_display_topology dpu_encoder_get_topology( > * Add dspps to the reservation requirements if ctm is requested > */ > if (intf_count == 2) > - topology.num_lm = 2; > + topology->num_lm = 2; > else if (!dpu_kms->catalog->caps->has_3d_merge) > - topology.num_lm = 1; > + topology->num_lm = 1; > else > - topology.num_lm = (mode->hdisplay > MAX_HDISPLAY_SPLIT) ? 2 : 1; > + topology->num_lm = (mode->hdisplay > MAX_HDISPLAY_SPLIT) ? 2 : 1; > > if (crtc_state->ctm) > - topology.num_dspp = topology.num_lm; > + topology->num_dspp = topology->num_lm; > > - topology.num_intf = intf_count; > + topology->num_intf = intf_count; > > if (dpu_enc->dsc) { > /* > @@ -585,12 +585,10 @@ static struct msm_display_topology dpu_encoder_get_topology( > * this is power optimal and can drive up to (including) 4k > * screens > */ > - topology.num_dsc = 2; > - topology.num_lm = 2; > - topology.num_intf = 1; > + topology->num_dsc = 2; > + topology->num_lm = 2; > + topology->num_intf = 1; > } > - > - return topology; > } > > static int dpu_encoder_virt_atomic_check( > @@ -602,7 +600,7 @@ static int dpu_encoder_virt_atomic_check( > struct msm_drm_private *priv; > struct dpu_kms *dpu_kms; > struct drm_display_mode *adj_mode; > - struct msm_display_topology topology; > + struct msm_display_topology *topology; > struct dpu_global_state *global_state; > int i = 0; > int ret = 0; > @@ -639,7 +637,9 @@ static int dpu_encoder_virt_atomic_check( > } > } > > - topology = dpu_encoder_get_topology(dpu_enc, dpu_kms, adj_mode, crtc_state); > + topology = &dpu_enc->topology; > + memset(topology, 0, sizeof (*topology)); > + dpu_encoder_get_topology(dpu_enc, dpu_kms, adj_mode, crtc_state, topology); > > /* > * Release and Allocate resources on every modeset > @@ -650,7 +650,7 @@ static int dpu_encoder_virt_atomic_check( > > if (!crtc_state->active_changed || crtc_state->enable) > ret = dpu_rm_reserve(&dpu_kms->rm, global_state, > - drm_enc, crtc_state, topology); > + drm_enc, crtc_state, *topology); > } > > trace_dpu_enc_atomic_check_flags(DRMID(drm_enc), adj_mode->flags);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index ecb87bc..2fdacf1 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -542,13 +542,13 @@ bool dpu_encoder_use_dsc_merge(struct drm_encoder *drm_enc) return (num_dsc > 0) && (num_dsc > intf_count); } -static struct msm_display_topology dpu_encoder_get_topology( +static void dpu_encoder_get_topology( struct dpu_encoder_virt *dpu_enc, struct dpu_kms *dpu_kms, struct drm_display_mode *mode, - struct drm_crtc_state *crtc_state) + struct drm_crtc_state *crtc_state, + struct msm_display_topology *topology) { - struct msm_display_topology topology = {0}; int i, intf_count = 0; for (i = 0; i < MAX_PHYS_ENCODERS_PER_VIRTUAL; i++) @@ -567,16 +567,16 @@ static struct msm_display_topology dpu_encoder_get_topology( * Add dspps to the reservation requirements if ctm is requested */ if (intf_count == 2) - topology.num_lm = 2; + topology->num_lm = 2; else if (!dpu_kms->catalog->caps->has_3d_merge) - topology.num_lm = 1; + topology->num_lm = 1; else - topology.num_lm = (mode->hdisplay > MAX_HDISPLAY_SPLIT) ? 2 : 1; + topology->num_lm = (mode->hdisplay > MAX_HDISPLAY_SPLIT) ? 2 : 1; if (crtc_state->ctm) - topology.num_dspp = topology.num_lm; + topology->num_dspp = topology->num_lm; - topology.num_intf = intf_count; + topology->num_intf = intf_count; if (dpu_enc->dsc) { /* @@ -585,12 +585,10 @@ static struct msm_display_topology dpu_encoder_get_topology( * this is power optimal and can drive up to (including) 4k * screens */ - topology.num_dsc = 2; - topology.num_lm = 2; - topology.num_intf = 1; + topology->num_dsc = 2; + topology->num_lm = 2; + topology->num_intf = 1; } - - return topology; } static int dpu_encoder_virt_atomic_check( @@ -602,7 +600,7 @@ static int dpu_encoder_virt_atomic_check( struct msm_drm_private *priv; struct dpu_kms *dpu_kms; struct drm_display_mode *adj_mode; - struct msm_display_topology topology; + struct msm_display_topology *topology; struct dpu_global_state *global_state; int i = 0; int ret = 0; @@ -639,7 +637,9 @@ static int dpu_encoder_virt_atomic_check( } } - topology = dpu_encoder_get_topology(dpu_enc, dpu_kms, adj_mode, crtc_state); + topology = &dpu_enc->topology; + memset(topology, 0, sizeof (*topology)); + dpu_encoder_get_topology(dpu_enc, dpu_kms, adj_mode, crtc_state, topology); /* * Release and Allocate resources on every modeset @@ -650,7 +650,7 @@ static int dpu_encoder_virt_atomic_check( if (!crtc_state->active_changed || crtc_state->enable) ret = dpu_rm_reserve(&dpu_kms->rm, global_state, - drm_enc, crtc_state, topology); + drm_enc, crtc_state, *topology); } trace_dpu_enc_atomic_check_flags(DRMID(drm_enc), adj_mode->flags);
At current implementation, topology configuration is thrown away after dpu_rm_reserve(). This patch save the topology so that it can be used for DSC related calculation later. Signed-off-by: Kuogee Hsieh <quic_khsieh@quicinc.com> --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 32 ++++++++++++++--------------- 1 file changed, 16 insertions(+), 16 deletions(-)