| Message ID | 20230405-add-dsc-support-v1-3-6bc6f03ae735@quicinc.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add DSC v1.2 Support for DSI | expand |
On 2023-05-02 18:19:14, Jessica Zhang wrote: > Add data_compress feature to DPU HW catalog. > > In DPU 7.x and later, there is a DATA_COMPRESS register that must be set > within the DPU INTF block for DSC to work. > > As core_rev (and related macros) was removed from the dpu_kms struct, the > most straightforward way to indicate the presence of this register would be > to have a flag in dpu_caps. This is a very generic name to have in the global dpu_caps for a very specific register on the INTF block since DPU >= 7.0.0, and I doubt any new catalog contributor will know how to fill this field. After all, DPU < 7.0.0 also has DCE but it is controlled via the PINGPONG block. Instead, how about having it as a DPU_INTF_DATA_COMPRESS (or similar) feature flag on the INTF block? We do the same for other (register related) features on the INTF block, and you did the same to disable DSC callbacks on PP in [1]. In fact it seems that the DSC/DCE (enablement) registers have been moved from PINGPONG to INTF in DPU 7.0.0. Can you clarify in the patch message for v2 that this is the case, and do the same in the linked PINGPONG patch? Perhaps these patches should be part of the same series as they do not seem DSI-specific. [1]: https://lore.kernel.org/linux-arm-msm/1683061382-32651-3-git-send-email-quic_khsieh@quicinc.com/ - Marijn > Signed-off-by: Jessica Zhang <quic_jesszhan@quicinc.com> > --- > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 1 + > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 1 + > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 1 + > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 1 + > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 1 + > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 ++ > 6 files changed, 7 insertions(+) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h > index f98c2a5b0e87..4160a35ff20f 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h > @@ -15,6 +15,7 @@ static const struct dpu_caps sm8350_dpu_caps = { > .has_dim_layer = true, > .has_idle_pc = true, > .has_3d_merge = true, > + .has_data_compress = true, > .max_linewidth = 4096, > .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, > }; > diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h > index 3fd0498ab420..23230841a0d1 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h > @@ -13,6 +13,7 @@ static const struct dpu_caps sc7280_dpu_caps = { > .qseed_type = DPU_SSPP_SCALER_QSEED4, > .has_dim_layer = true, > .has_idle_pc = true, > + .has_data_compress = true, > .max_linewidth = 2400, > .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, > }; > diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h > index ce583eb14b06..c990406e4bca 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h > @@ -15,6 +15,7 @@ static const struct dpu_caps sc8280xp_dpu_caps = { > .has_dim_layer = true, > .has_idle_pc = true, > .has_3d_merge = true, > + .has_data_compress = true, > .max_linewidth = 5120, > .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, > }; > diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h > index 3950e7b946a5..7094640e2fbf 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h > @@ -15,6 +15,7 @@ static const struct dpu_caps sm8450_dpu_caps = { > .has_dim_layer = true, > .has_idle_pc = true, > .has_3d_merge = true, > + .has_data_compress = true, > .max_linewidth = 5120, > .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, > }; > diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h > index 1b3f5424aea8..970049559e02 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h > @@ -15,6 +15,7 @@ static const struct dpu_caps sm8550_dpu_caps = { > .has_dim_layer = true, > .has_idle_pc = true, > .has_3d_merge = true, > + .has_data_compress = true, > .max_linewidth = 5120, > .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, > }; > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h > index b410a85c109c..c5bbd4ad6da8 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h > @@ -380,6 +380,7 @@ struct dpu_rotation_cfg { > * @has_dim_layer dim layer feature status > * @has_idle_pc indicate if idle power collapse feature is supported > * @has_3d_merge indicate if 3D merge is supported > + * @has_data_compress indicate if data compression is supported > * @max_linewidth max linewidth for sspp > * @pixel_ram_size size of latency hiding and de-tiling buffer in bytes > * @max_hdeci_exp max horizontal decimation supported (max is 2^value) > @@ -393,6 +394,7 @@ struct dpu_caps { > bool has_dim_layer; > bool has_idle_pc; > bool has_3d_merge; > + bool has_data_compress; > /* SSPP limits */ > u32 max_linewidth; > u32 pixel_ram_size; > > -- > 2.40.1 >
On 5/3/2023 12:07 AM, Marijn Suijten wrote: > On 2023-05-02 18:19:14, Jessica Zhang wrote: >> Add data_compress feature to DPU HW catalog. >> >> In DPU 7.x and later, there is a DATA_COMPRESS register that must be set >> within the DPU INTF block for DSC to work. >> >> As core_rev (and related macros) was removed from the dpu_kms struct, the >> most straightforward way to indicate the presence of this register would be >> to have a flag in dpu_caps. > > This is a very generic name to have in the global dpu_caps for a very > specific register on the INTF block since DPU >= 7.0.0, and I doubt any > new catalog contributor will know how to fill this field. After all, > DPU < 7.0.0 also has DCE but it is controlled via the PINGPONG block. > > Instead, how about having it as a DPU_INTF_DATA_COMPRESS (or similar) > feature flag on the INTF block? We do the same for other (register > related) features on the INTF block, and you did the same to disable DSC > callbacks on PP in [1]. Hi Marijn, Sounds good. > > In fact it seems that the DSC/DCE (enablement) registers have been moved > from PINGPONG to INTF in DPU 7.0.0. Can you clarify in the patch > message for v2 that this is the case, and do the same in the linked > PINGPONG patch? Perhaps these patches should be part of the same series > as they do not seem DSI-specific. Will make a note of the PP to INTF change in the commit message. I would prefer to keep this patch in this series is because it is needed for DSI over command mode to work and the subsequent patch is specifically for command mode. Thanks, Jessica Zhang > > [1]: https://lore.kernel.org/linux-arm-msm/1683061382-32651-3-git-send-email-quic_khsieh@quicinc.com/ > > - Marijn > >> Signed-off-by: Jessica Zhang <quic_jesszhan@quicinc.com> >> --- >> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 1 + >> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 1 + >> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 1 + >> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 1 + >> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 1 + >> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 ++ >> 6 files changed, 7 insertions(+) >> >> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h >> index f98c2a5b0e87..4160a35ff20f 100644 >> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h >> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h >> @@ -15,6 +15,7 @@ static const struct dpu_caps sm8350_dpu_caps = { >> .has_dim_layer = true, >> .has_idle_pc = true, >> .has_3d_merge = true, >> + .has_data_compress = true, >> .max_linewidth = 4096, >> .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, >> }; >> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h >> index 3fd0498ab420..23230841a0d1 100644 >> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h >> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h >> @@ -13,6 +13,7 @@ static const struct dpu_caps sc7280_dpu_caps = { >> .qseed_type = DPU_SSPP_SCALER_QSEED4, >> .has_dim_layer = true, >> .has_idle_pc = true, >> + .has_data_compress = true, >> .max_linewidth = 2400, >> .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, >> }; >> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h >> index ce583eb14b06..c990406e4bca 100644 >> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h >> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h >> @@ -15,6 +15,7 @@ static const struct dpu_caps sc8280xp_dpu_caps = { >> .has_dim_layer = true, >> .has_idle_pc = true, >> .has_3d_merge = true, >> + .has_data_compress = true, >> .max_linewidth = 5120, >> .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, >> }; >> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h >> index 3950e7b946a5..7094640e2fbf 100644 >> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h >> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h >> @@ -15,6 +15,7 @@ static const struct dpu_caps sm8450_dpu_caps = { >> .has_dim_layer = true, >> .has_idle_pc = true, >> .has_3d_merge = true, >> + .has_data_compress = true, >> .max_linewidth = 5120, >> .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, >> }; >> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h >> index 1b3f5424aea8..970049559e02 100644 >> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h >> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h >> @@ -15,6 +15,7 @@ static const struct dpu_caps sm8550_dpu_caps = { >> .has_dim_layer = true, >> .has_idle_pc = true, >> .has_3d_merge = true, >> + .has_data_compress = true, >> .max_linewidth = 5120, >> .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, >> }; >> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h >> index b410a85c109c..c5bbd4ad6da8 100644 >> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h >> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h >> @@ -380,6 +380,7 @@ struct dpu_rotation_cfg { >> * @has_dim_layer dim layer feature status >> * @has_idle_pc indicate if idle power collapse feature is supported >> * @has_3d_merge indicate if 3D merge is supported >> + * @has_data_compress indicate if data compression is supported >> * @max_linewidth max linewidth for sspp >> * @pixel_ram_size size of latency hiding and de-tiling buffer in bytes >> * @max_hdeci_exp max horizontal decimation supported (max is 2^value) >> @@ -393,6 +394,7 @@ struct dpu_caps { >> bool has_dim_layer; >> bool has_idle_pc; >> bool has_3d_merge; >> + bool has_data_compress; >> /* SSPP limits */ >> u32 max_linewidth; >> u32 pixel_ram_size; >> >> -- >> 2.40.1 >>
Hi Jessica, On 2023-05-03 12:03:40, Jessica Zhang wrote: > > > On 5/3/2023 12:07 AM, Marijn Suijten wrote: > > On 2023-05-02 18:19:14, Jessica Zhang wrote: > >> Add data_compress feature to DPU HW catalog. > >> > >> In DPU 7.x and later, there is a DATA_COMPRESS register that must be set > >> within the DPU INTF block for DSC to work. > >> > >> As core_rev (and related macros) was removed from the dpu_kms struct, the > >> most straightforward way to indicate the presence of this register would be > >> to have a flag in dpu_caps. > > > > This is a very generic name to have in the global dpu_caps for a very > > specific register on the INTF block since DPU >= 7.0.0, and I doubt any > > new catalog contributor will know how to fill this field. After all, > > DPU < 7.0.0 also has DCE but it is controlled via the PINGPONG block. > > > > Instead, how about having it as a DPU_INTF_DATA_COMPRESS (or similar) > > feature flag on the INTF block? We do the same for other (register > > related) features on the INTF block, and you did the same to disable DSC > > callbacks on PP in [1]. (Note: I said "you" but meant Kuogee) > Hi Marijn, > > Sounds good. > > > > > In fact it seems that the DSC/DCE (enablement) registers have been moved > > from PINGPONG to INTF in DPU 7.0.0. Can you clarify in the patch > > message for v2 that this is the case, and do the same in the linked > > PINGPONG patch? Perhaps these patches should be part of the same series > > as they do not seem DSI-specific. > > Will make a note of the PP to INTF change in the commit message. Thanks. > I would prefer to keep this patch in this series is because it is needed > for DSI over command mode to work and the subsequent patch is > specifically for command mode. That is fine, but do mention this in the commit message if it is relevant here. Otherwise only mention it as part of patch 4/4. - Marijn
On 5/3/2023 4:03 PM, Marijn Suijten wrote: > Hi Jessica, > > On 2023-05-03 12:03:40, Jessica Zhang wrote: >> >> >> On 5/3/2023 12:07 AM, Marijn Suijten wrote: >>> On 2023-05-02 18:19:14, Jessica Zhang wrote: >>>> Add data_compress feature to DPU HW catalog. >>>> >>>> In DPU 7.x and later, there is a DATA_COMPRESS register that must be set >>>> within the DPU INTF block for DSC to work. >>>> >>>> As core_rev (and related macros) was removed from the dpu_kms struct, the >>>> most straightforward way to indicate the presence of this register would be >>>> to have a flag in dpu_caps. >>> >>> This is a very generic name to have in the global dpu_caps for a very >>> specific register on the INTF block since DPU >= 7.0.0, and I doubt any >>> new catalog contributor will know how to fill this field. After all, >>> DPU < 7.0.0 also has DCE but it is controlled via the PINGPONG block. >>> >>> Instead, how about having it as a DPU_INTF_DATA_COMPRESS (or similar) >>> feature flag on the INTF block? We do the same for other (register >>> related) features on the INTF block, and you did the same to disable DSC >>> callbacks on PP in [1]. > > (Note: I said "you" but meant Kuogee) > >> Hi Marijn, >> >> Sounds good. >> >>> >>> In fact it seems that the DSC/DCE (enablement) registers have been moved >>> from PINGPONG to INTF in DPU 7.0.0. Can you clarify in the patch >>> message for v2 that this is the case, and do the same in the linked >>> PINGPONG patch? Perhaps these patches should be part of the same series >>> as they do not seem DSI-specific. >> >> Will make a note of the PP to INTF change in the commit message. > > Thanks. > >> I would prefer to keep this patch in this series is because it is needed >> for DSI over command mode to work and the subsequent patch is >> specifically for command mode. > > That is fine, but do mention this in the commit message if it is > relevant here. Otherwise only mention it as part of patch 4/4. Acked. Thanks, Jessica Zhang > > - Marijn
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h index f98c2a5b0e87..4160a35ff20f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h @@ -15,6 +15,7 @@ static const struct dpu_caps sm8350_dpu_caps = { .has_dim_layer = true, .has_idle_pc = true, .has_3d_merge = true, + .has_data_compress = true, .max_linewidth = 4096, .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h index 3fd0498ab420..23230841a0d1 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h @@ -13,6 +13,7 @@ static const struct dpu_caps sc7280_dpu_caps = { .qseed_type = DPU_SSPP_SCALER_QSEED4, .has_dim_layer = true, .has_idle_pc = true, + .has_data_compress = true, .max_linewidth = 2400, .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h index ce583eb14b06..c990406e4bca 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h @@ -15,6 +15,7 @@ static const struct dpu_caps sc8280xp_dpu_caps = { .has_dim_layer = true, .has_idle_pc = true, .has_3d_merge = true, + .has_data_compress = true, .max_linewidth = 5120, .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h index 3950e7b946a5..7094640e2fbf 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h @@ -15,6 +15,7 @@ static const struct dpu_caps sm8450_dpu_caps = { .has_dim_layer = true, .has_idle_pc = true, .has_3d_merge = true, + .has_data_compress = true, .max_linewidth = 5120, .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h index 1b3f5424aea8..970049559e02 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h @@ -15,6 +15,7 @@ static const struct dpu_caps sm8550_dpu_caps = { .has_dim_layer = true, .has_idle_pc = true, .has_3d_merge = true, + .has_data_compress = true, .max_linewidth = 5120, .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h index b410a85c109c..c5bbd4ad6da8 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -380,6 +380,7 @@ struct dpu_rotation_cfg { * @has_dim_layer dim layer feature status * @has_idle_pc indicate if idle power collapse feature is supported * @has_3d_merge indicate if 3D merge is supported + * @has_data_compress indicate if data compression is supported * @max_linewidth max linewidth for sspp * @pixel_ram_size size of latency hiding and de-tiling buffer in bytes * @max_hdeci_exp max horizontal decimation supported (max is 2^value) @@ -393,6 +394,7 @@ struct dpu_caps { bool has_dim_layer; bool has_idle_pc; bool has_3d_merge; + bool has_data_compress; /* SSPP limits */ u32 max_linewidth; u32 pixel_ram_size;
Add data_compress feature to DPU HW catalog. In DPU 7.x and later, there is a DATA_COMPRESS register that must be set within the DPU INTF block for DSC to work. As core_rev (and related macros) was removed from the dpu_kms struct, the most straightforward way to indicate the presence of this register would be to have a flag in dpu_caps. Signed-off-by: Jessica Zhang <quic_jesszhan@quicinc.com> --- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 1 + drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 1 + drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 1 + drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 1 + drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 ++ 6 files changed, 7 insertions(+)