| Message ID | 20230329-rfc-msm-dsc-helper-v6-4-cb7f59f0f7fb@quicinc.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Introduce MSM-specific DSC helpers | expand |
On 2023-04-12 16:25:18, Jessica Zhang wrote: > Correct the math for slice_last_group_size so that it matches the > calculations downstream. > > Changes in v3: > - Reworded slice_last_group_size calculation to > `(dsc->slice_width + 2) % 3` > > Fixes: c110cfd1753e ("drm/msm/disp/dpu1: Add support for DSC") > Signed-off-by: Jessica Zhang <quic_jesszhan@quicinc.com> > Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > --- > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c | 5 +++-- > 1 file changed, 3 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c > index b952f7d2b7f5..ff1c8f92fb20 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c > @@ -56,9 +56,10 @@ static void dpu_hw_dsc_config(struct dpu_hw_dsc *hw_dsc, > if (is_cmd_mode) > initial_lines += 1; > > - slice_last_group_size = 3 - (dsc->slice_width % 3); > + slice_last_group_size = (dsc->slice_width + 2) % 3; > + > data = (initial_lines << 20); > - data |= ((slice_last_group_size - 1) << 18); > + data |= (slice_last_group_size << 18); Agreed, this matches the calculation found in newer downstream. This older calculation is only present in an older fbdev driver, and was working for the only panel I was able to test because the new and the old calculation result in the same value: 3 - (720 % 3) - 1 = 2 (720 + 2) % 3 = 2 The other two outcomes are flipped, and match the downstream switch-case on slice_width % 3: 0 -> 2 1 -> 0 2 -> 1 More importantly it is one of the fixes necessary to get DSC working on my SM8150 and SM8250 devices [1]. Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> Thanks! - Marijn [1]: https://gitlab.freedesktop.org/drm/msm/-/issues/24#note_1899310 > /* bpp is 6.4 format, 4 LSBs bits are for fractional part */ > data |= (dsc->bits_per_pixel << 8); > data |= (dsc->block_pred_enable << 7); > > -- > 2.40.0 >
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c index b952f7d2b7f5..ff1c8f92fb20 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c @@ -56,9 +56,10 @@ static void dpu_hw_dsc_config(struct dpu_hw_dsc *hw_dsc, if (is_cmd_mode) initial_lines += 1; - slice_last_group_size = 3 - (dsc->slice_width % 3); + slice_last_group_size = (dsc->slice_width + 2) % 3; + data = (initial_lines << 20); - data |= ((slice_last_group_size - 1) << 18); + data |= (slice_last_group_size << 18); /* bpp is 6.4 format, 4 LSBs bits are for fractional part */ data |= (dsc->bits_per_pixel << 8); data |= (dsc->block_pred_enable << 7);
Correct the math for slice_last_group_size so that it matches the calculations downstream. Changes in v3: - Reworded slice_last_group_size calculation to `(dsc->slice_width + 2) % 3` Fixes: c110cfd1753e ("drm/msm/disp/dpu1: Add support for DSC") Signed-off-by: Jessica Zhang <quic_jesszhan@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-)