| Message ID | 20230508183428.1893357-1-pmalani@chromium.org (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | c9f9c6c875d14a107dabcf4579fcab95ed30af31 |
| Headers | show |
| Series | platform/chrome: cros_typec_switch: Add Pin D support | expand |
On Mon, May 08, 2023 at 06:34:27PM +0000, Prashant Malani wrote: > The ChromeOS EC's mux interface allows us to specify whether the port > should be configured for Pin Assignment D in DisplayPort alternate mode > (i.e 2 lanes USB + 2 lanes DP). Update the function that determines mux > state to account for Pin Assignment D and return the appropriate mux > setting. > > Cc: Heikki Krogerus <heikki.krogerus@linux.intel.com> > Signed-off-by: Prashant Malani <pmalani@chromium.org> Acked-by: Heikki Krogerus <heikki.krogerus@linux.intel.com> > --- > drivers/platform/chrome/cros_typec_switch.c | 11 ++++++++--- > 1 file changed, 8 insertions(+), 3 deletions(-) > > diff --git a/drivers/platform/chrome/cros_typec_switch.c b/drivers/platform/chrome/cros_typec_switch.c > index 752720483753..0eefdcf14d63 100644 > --- a/drivers/platform/chrome/cros_typec_switch.c > +++ b/drivers/platform/chrome/cros_typec_switch.c > @@ -51,13 +51,18 @@ static int cros_typec_cmd_mux_set(struct cros_typec_switch_data *sdata, int port > static int cros_typec_get_mux_state(unsigned long mode, struct typec_altmode *alt) > { > int ret = -EOPNOTSUPP; > + u8 pin_assign; > > - if (mode == TYPEC_STATE_SAFE) > + if (mode == TYPEC_STATE_SAFE) { > ret = USB_PD_MUX_SAFE_MODE; > - else if (mode == TYPEC_STATE_USB) > + } else if (mode == TYPEC_STATE_USB) { > ret = USB_PD_MUX_USB_ENABLED; > - else if (alt && alt->svid == USB_TYPEC_DP_SID) > + } else if (alt && alt->svid == USB_TYPEC_DP_SID) { > ret = USB_PD_MUX_DP_ENABLED; > + pin_assign = mode - TYPEC_STATE_MODAL; > + if (pin_assign & DP_PIN_ASSIGN_D) > + ret |= USB_PD_MUX_USB_ENABLED; > + } > > return ret; > } thanks,
Hello: This patch was applied to chrome-platform/linux.git (for-kernelci) by Prashant Malani <pmalani@chromium.org>: On Mon, 8 May 2023 18:34:27 +0000 you wrote: > The ChromeOS EC's mux interface allows us to specify whether the port > should be configured for Pin Assignment D in DisplayPort alternate mode > (i.e 2 lanes USB + 2 lanes DP). Update the function that determines mux > state to account for Pin Assignment D and return the appropriate mux > setting. > > Cc: Heikki Krogerus <heikki.krogerus@linux.intel.com> > Signed-off-by: Prashant Malani <pmalani@chromium.org> > > [...] Here is the summary with links: - platform/chrome: cros_typec_switch: Add Pin D support https://git.kernel.org/chrome-platform/c/c9f9c6c875d1 You are awesome, thank you!
Hello: This patch was applied to chrome-platform/linux.git (for-next) by Prashant Malani <pmalani@chromium.org>: On Mon, 8 May 2023 18:34:27 +0000 you wrote: > The ChromeOS EC's mux interface allows us to specify whether the port > should be configured for Pin Assignment D in DisplayPort alternate mode > (i.e 2 lanes USB + 2 lanes DP). Update the function that determines mux > state to account for Pin Assignment D and return the appropriate mux > setting. > > Cc: Heikki Krogerus <heikki.krogerus@linux.intel.com> > Signed-off-by: Prashant Malani <pmalani@chromium.org> > > [...] Here is the summary with links: - platform/chrome: cros_typec_switch: Add Pin D support https://git.kernel.org/chrome-platform/c/c9f9c6c875d1 You are awesome, thank you!
diff --git a/drivers/platform/chrome/cros_typec_switch.c b/drivers/platform/chrome/cros_typec_switch.c index 752720483753..0eefdcf14d63 100644 --- a/drivers/platform/chrome/cros_typec_switch.c +++ b/drivers/platform/chrome/cros_typec_switch.c @@ -51,13 +51,18 @@ static int cros_typec_cmd_mux_set(struct cros_typec_switch_data *sdata, int port static int cros_typec_get_mux_state(unsigned long mode, struct typec_altmode *alt) { int ret = -EOPNOTSUPP; + u8 pin_assign; - if (mode == TYPEC_STATE_SAFE) + if (mode == TYPEC_STATE_SAFE) { ret = USB_PD_MUX_SAFE_MODE; - else if (mode == TYPEC_STATE_USB) + } else if (mode == TYPEC_STATE_USB) { ret = USB_PD_MUX_USB_ENABLED; - else if (alt && alt->svid == USB_TYPEC_DP_SID) + } else if (alt && alt->svid == USB_TYPEC_DP_SID) { ret = USB_PD_MUX_DP_ENABLED; + pin_assign = mode - TYPEC_STATE_MODAL; + if (pin_assign & DP_PIN_ASSIGN_D) + ret |= USB_PD_MUX_USB_ENABLED; + } return ret; }
The ChromeOS EC's mux interface allows us to specify whether the port should be configured for Pin Assignment D in DisplayPort alternate mode (i.e 2 lanes USB + 2 lanes DP). Update the function that determines mux state to account for Pin Assignment D and return the appropriate mux setting. Cc: Heikki Krogerus <heikki.krogerus@linux.intel.com> Signed-off-by: Prashant Malani <pmalani@chromium.org> --- drivers/platform/chrome/cros_typec_switch.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-)