| Message ID | 1678164097-13247-7-git-send-email-quic_mmanikan@quicinc.com (mailing list archive) |
|---|---|
| State | Changes Requested, archived |
| Headers | show |
| Series | Add multipd remoteproc support | expand |
On 3/7/2023 10:11 AM, Manikanta Mylavarapu wrote: > Some of the clocks required for q6/wcss bring up > are missing. So this patch adds clocks. > > Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com> > --- > drivers/clk/qcom/gcc-ipq9574.c | 119 +++++++++++++++++++++++++++++++++ > 1 file changed, 119 insertions(+) > > diff --git a/drivers/clk/qcom/gcc-ipq9574.c b/drivers/clk/qcom/gcc-ipq9574.c > index 1bf33d582dc2..355f2e12d9c6 100644 > --- a/drivers/clk/qcom/gcc-ipq9574.c > +++ b/drivers/clk/qcom/gcc-ipq9574.c > @@ -2697,6 +2697,22 @@ static struct clk_branch gcc_wcss_acmt_clk = { > }, > }; > > +static struct clk_branch gcc_wcss_ahb_s_clk = { > + .halt_reg = 0x25060, > + .clkr = { > + .enable_reg = 0x25060, > + .enable_mask = BIT(0), > + .hw.init = &(struct clk_init_data){ > + .name = "gcc_wcss_ahb_s_clk", > + .parent_hws = (const struct clk_hw *[]){ > + &wcss_ahb_clk_src.clkr.hw }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > static struct clk_branch gcc_sys_noc_wcss_ahb_clk = { > .halt_reg = 0x2e030, > .clkr = { > @@ -2734,6 +2750,22 @@ static struct clk_rcg2 wcss_axi_m_clk_src = { > }, > }; > > +static struct clk_branch gcc_wcss_axi_m_clk = { > + .halt_reg = 0x25064, > + .clkr = { > + .enable_reg = 0x25064, > + .enable_mask = BIT(0), > + .hw.init = &(struct clk_init_data){ > + .name = "gcc_wcss_axi_m_clk", > + .parent_hws = (const struct clk_hw *[]){ > + &wcss_axi_m_clk_src.clkr.hw }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > static struct clk_branch gcc_anoc_wcss_axi_m_clk = { > .halt_reg = 0x2e0a8, > .clkr = { > @@ -2803,6 +2835,22 @@ static struct clk_branch gcc_wcss_dbg_ifc_atb_clk = { > }, > }; > > +static struct clk_branch gcc_wcss_dbg_ifc_atb_bdg_clk = { > + .halt_reg = 0x2504C, > + .clkr = { > + .enable_reg = 0x2504C, > + .enable_mask = BIT(0), > + .hw.init = &(struct clk_init_data){ > + .name = "gcc_wcss_dbg_ifc_atb_bdg_clk", > + .parent_hws = (const struct clk_hw *[]){ > + &qdss_at_clk_src.clkr.hw }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > static struct clk_branch gcc_nssnoc_atb_clk = { > .halt_reg = 0x17014, > .clkr = { > @@ -3073,6 +3121,22 @@ static struct clk_branch gcc_wcss_dbg_ifc_nts_clk = { > }, > }; > > +static struct clk_branch gcc_wcss_dbg_ifc_nts_bdg_clk = { > + .halt_reg = 0x25050, > + .clkr = { > + .enable_reg = 0x25050, > + .enable_mask = BIT(0), > + .hw.init = &(struct clk_init_data){ > + .name = "gcc_wcss_dbg_ifc_nts_bdg_clk", > + .parent_hws = (const struct clk_hw *[]){ > + &qdss_tsctr_div2_clk_src.hw }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > static struct clk_branch gcc_qdss_tsctr_div2_clk = { > .halt_reg = 0x2d044, > .clkr = { > @@ -3315,6 +3379,38 @@ static struct clk_branch gcc_wcss_dbg_ifc_dapbus_clk = { > }, > }; > > +static struct clk_branch gcc_wcss_dbg_ifc_apb_bdg_clk = { > + .halt_reg = 0x25048, > + .clkr = { > + .enable_reg = 0x25048, > + .enable_mask = BIT(0), > + .hw.init = &(struct clk_init_data){ > + .name = "gcc_wcss_dbg_ifc_apb_bdg_clk", > + .parent_hws = (const struct clk_hw *[]){ > + &qdss_dap_sync_clk_src.hw }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch gcc_wcss_dbg_ifc_dapbus_bdg_clk = { > + .halt_reg = 0x25054, > + .clkr = { > + .enable_reg = 0x25054, > + .enable_mask = BIT(0), > + .hw.init = &(struct clk_init_data){ > + .name = "gcc_wcss_dbg_ifc_dapbus_bdg_clk", > + .parent_hws = (const struct clk_hw *[]){ > + &qdss_dap_sync_clk_src.hw }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > static struct clk_branch gcc_qdss_dap_clk = { > .halt_reg = 0x2d058, > .clkr = { > @@ -3513,6 +3609,22 @@ static struct clk_rcg2 q6_axim2_clk_src = { > }, > }; > > +static struct clk_branch gcc_q6_axim2_clk = { > + .halt_reg = 0x25010, > + .clkr = { > + .enable_reg = 0x25010, > + .enable_mask = BIT(0), > + .hw.init = &(struct clk_init_data){ > + .name = "gcc_q6_axim2_clk", > + .parent_hws = (const struct clk_hw *[]){ > + &q6_axim2_clk_src.clkr.hw }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + These clocks does not seem to be used in the driver, where are they used ? Regards, Sricharan
On 3/7/2023 12:58 PM, Sricharan Ramabadhran wrote: > > > On 3/7/2023 10:11 AM, Manikanta Mylavarapu wrote: >> Some of the clocks required for q6/wcss bring up >> are missing. So this patch adds clocks. >> >> Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com> >> --- >> drivers/clk/qcom/gcc-ipq9574.c | 119 +++++++++++++++++++++++++++++++++ >> 1 file changed, 119 insertions(+) >> >> diff --git a/drivers/clk/qcom/gcc-ipq9574.c >> b/drivers/clk/qcom/gcc-ipq9574.c >> index 1bf33d582dc2..355f2e12d9c6 100644 >> --- a/drivers/clk/qcom/gcc-ipq9574.c >> +++ b/drivers/clk/qcom/gcc-ipq9574.c >> @@ -2697,6 +2697,22 @@ static struct clk_branch gcc_wcss_acmt_clk = { >> }, >> }; >> +static struct clk_branch gcc_wcss_ahb_s_clk = { >> + .halt_reg = 0x25060, >> + .clkr = { >> + .enable_reg = 0x25060, >> + .enable_mask = BIT(0), >> + .hw.init = &(struct clk_init_data){ >> + .name = "gcc_wcss_ahb_s_clk", >> + .parent_hws = (const struct clk_hw *[]){ >> + &wcss_ahb_clk_src.clkr.hw }, >> + .num_parents = 1, >> + .flags = CLK_SET_RATE_PARENT, >> + .ops = &clk_branch2_ops, >> + }, >> + }, >> +}; >> + >> static struct clk_branch gcc_sys_noc_wcss_ahb_clk = { >> .halt_reg = 0x2e030, >> .clkr = { >> @@ -2734,6 +2750,22 @@ static struct clk_rcg2 wcss_axi_m_clk_src = { >> }, >> }; >> +static struct clk_branch gcc_wcss_axi_m_clk = { >> + .halt_reg = 0x25064, >> + .clkr = { >> + .enable_reg = 0x25064, >> + .enable_mask = BIT(0), >> + .hw.init = &(struct clk_init_data){ >> + .name = "gcc_wcss_axi_m_clk", >> + .parent_hws = (const struct clk_hw *[]){ >> + &wcss_axi_m_clk_src.clkr.hw }, >> + .num_parents = 1, >> + .flags = CLK_SET_RATE_PARENT, >> + .ops = &clk_branch2_ops, >> + }, >> + }, >> +}; >> + >> static struct clk_branch gcc_anoc_wcss_axi_m_clk = { >> .halt_reg = 0x2e0a8, >> .clkr = { >> @@ -2803,6 +2835,22 @@ static struct clk_branch >> gcc_wcss_dbg_ifc_atb_clk = { >> }, >> }; >> +static struct clk_branch gcc_wcss_dbg_ifc_atb_bdg_clk = { >> + .halt_reg = 0x2504C, >> + .clkr = { >> + .enable_reg = 0x2504C, >> + .enable_mask = BIT(0), >> + .hw.init = &(struct clk_init_data){ >> + .name = "gcc_wcss_dbg_ifc_atb_bdg_clk", >> + .parent_hws = (const struct clk_hw *[]){ >> + &qdss_at_clk_src.clkr.hw }, >> + .num_parents = 1, >> + .flags = CLK_SET_RATE_PARENT, >> + .ops = &clk_branch2_ops, >> + }, >> + }, >> +}; >> + >> static struct clk_branch gcc_nssnoc_atb_clk = { >> .halt_reg = 0x17014, >> .clkr = { >> @@ -3073,6 +3121,22 @@ static struct clk_branch >> gcc_wcss_dbg_ifc_nts_clk = { >> }, >> }; >> +static struct clk_branch gcc_wcss_dbg_ifc_nts_bdg_clk = { >> + .halt_reg = 0x25050, >> + .clkr = { >> + .enable_reg = 0x25050, >> + .enable_mask = BIT(0), >> + .hw.init = &(struct clk_init_data){ >> + .name = "gcc_wcss_dbg_ifc_nts_bdg_clk", >> + .parent_hws = (const struct clk_hw *[]){ >> + &qdss_tsctr_div2_clk_src.hw }, >> + .num_parents = 1, >> + .flags = CLK_SET_RATE_PARENT, >> + .ops = &clk_branch2_ops, >> + }, >> + }, >> +}; >> + >> static struct clk_branch gcc_qdss_tsctr_div2_clk = { >> .halt_reg = 0x2d044, >> .clkr = { >> @@ -3315,6 +3379,38 @@ static struct clk_branch >> gcc_wcss_dbg_ifc_dapbus_clk = { >> }, >> }; >> +static struct clk_branch gcc_wcss_dbg_ifc_apb_bdg_clk = { >> + .halt_reg = 0x25048, >> + .clkr = { >> + .enable_reg = 0x25048, >> + .enable_mask = BIT(0), >> + .hw.init = &(struct clk_init_data){ >> + .name = "gcc_wcss_dbg_ifc_apb_bdg_clk", >> + .parent_hws = (const struct clk_hw *[]){ >> + &qdss_dap_sync_clk_src.hw }, >> + .num_parents = 1, >> + .flags = CLK_SET_RATE_PARENT, >> + .ops = &clk_branch2_ops, >> + }, >> + }, >> +}; >> + >> +static struct clk_branch gcc_wcss_dbg_ifc_dapbus_bdg_clk = { >> + .halt_reg = 0x25054, >> + .clkr = { >> + .enable_reg = 0x25054, >> + .enable_mask = BIT(0), >> + .hw.init = &(struct clk_init_data){ >> + .name = "gcc_wcss_dbg_ifc_dapbus_bdg_clk", >> + .parent_hws = (const struct clk_hw *[]){ >> + &qdss_dap_sync_clk_src.hw }, >> + .num_parents = 1, >> + .flags = CLK_SET_RATE_PARENT, >> + .ops = &clk_branch2_ops, >> + }, >> + }, >> +}; >> + >> static struct clk_branch gcc_qdss_dap_clk = { >> .halt_reg = 0x2d058, >> .clkr = { >> @@ -3513,6 +3609,22 @@ static struct clk_rcg2 q6_axim2_clk_src = { >> }, >> }; >> +static struct clk_branch gcc_q6_axim2_clk = { >> + .halt_reg = 0x25010, >> + .clkr = { >> + .enable_reg = 0x25010, >> + .enable_mask = BIT(0), >> + .hw.init = &(struct clk_init_data){ >> + .name = "gcc_q6_axim2_clk", >> + .parent_hws = (const struct clk_hw *[]){ >> + &q6_axim2_clk_src.clkr.hw }, >> + .num_parents = 1, >> + .flags = CLK_SET_RATE_PARENT, >> + .ops = &clk_branch2_ops, >> + }, >> + }, >> +}; >> + > > These clocks does not seem to be used in the driver, where are they used ? > > Regards, > Sricharan Clocks in multipd architecture will be handled by QDSP6 firmware. So i am going to remove clock handling and drop this patch. Thanks & Regards, Manikanta.
diff --git a/drivers/clk/qcom/gcc-ipq9574.c b/drivers/clk/qcom/gcc-ipq9574.c index 1bf33d582dc2..355f2e12d9c6 100644 --- a/drivers/clk/qcom/gcc-ipq9574.c +++ b/drivers/clk/qcom/gcc-ipq9574.c @@ -2697,6 +2697,22 @@ static struct clk_branch gcc_wcss_acmt_clk = { }, }; +static struct clk_branch gcc_wcss_ahb_s_clk = { + .halt_reg = 0x25060, + .clkr = { + .enable_reg = 0x25060, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_wcss_ahb_s_clk", + .parent_hws = (const struct clk_hw *[]){ + &wcss_ahb_clk_src.clkr.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_branch gcc_sys_noc_wcss_ahb_clk = { .halt_reg = 0x2e030, .clkr = { @@ -2734,6 +2750,22 @@ static struct clk_rcg2 wcss_axi_m_clk_src = { }, }; +static struct clk_branch gcc_wcss_axi_m_clk = { + .halt_reg = 0x25064, + .clkr = { + .enable_reg = 0x25064, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_wcss_axi_m_clk", + .parent_hws = (const struct clk_hw *[]){ + &wcss_axi_m_clk_src.clkr.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_branch gcc_anoc_wcss_axi_m_clk = { .halt_reg = 0x2e0a8, .clkr = { @@ -2803,6 +2835,22 @@ static struct clk_branch gcc_wcss_dbg_ifc_atb_clk = { }, }; +static struct clk_branch gcc_wcss_dbg_ifc_atb_bdg_clk = { + .halt_reg = 0x2504C, + .clkr = { + .enable_reg = 0x2504C, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_wcss_dbg_ifc_atb_bdg_clk", + .parent_hws = (const struct clk_hw *[]){ + &qdss_at_clk_src.clkr.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_branch gcc_nssnoc_atb_clk = { .halt_reg = 0x17014, .clkr = { @@ -3073,6 +3121,22 @@ static struct clk_branch gcc_wcss_dbg_ifc_nts_clk = { }, }; +static struct clk_branch gcc_wcss_dbg_ifc_nts_bdg_clk = { + .halt_reg = 0x25050, + .clkr = { + .enable_reg = 0x25050, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_wcss_dbg_ifc_nts_bdg_clk", + .parent_hws = (const struct clk_hw *[]){ + &qdss_tsctr_div2_clk_src.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_branch gcc_qdss_tsctr_div2_clk = { .halt_reg = 0x2d044, .clkr = { @@ -3315,6 +3379,38 @@ static struct clk_branch gcc_wcss_dbg_ifc_dapbus_clk = { }, }; +static struct clk_branch gcc_wcss_dbg_ifc_apb_bdg_clk = { + .halt_reg = 0x25048, + .clkr = { + .enable_reg = 0x25048, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_wcss_dbg_ifc_apb_bdg_clk", + .parent_hws = (const struct clk_hw *[]){ + &qdss_dap_sync_clk_src.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_wcss_dbg_ifc_dapbus_bdg_clk = { + .halt_reg = 0x25054, + .clkr = { + .enable_reg = 0x25054, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_wcss_dbg_ifc_dapbus_bdg_clk", + .parent_hws = (const struct clk_hw *[]){ + &qdss_dap_sync_clk_src.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_branch gcc_qdss_dap_clk = { .halt_reg = 0x2d058, .clkr = { @@ -3513,6 +3609,22 @@ static struct clk_rcg2 q6_axim2_clk_src = { }, }; +static struct clk_branch gcc_q6_axim2_clk = { + .halt_reg = 0x25010, + .clkr = { + .enable_reg = 0x25010, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_q6_axim2_clk", + .parent_hws = (const struct clk_hw *[]){ + &q6_axim2_clk_src.clkr.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + static const struct freq_tbl ftbl_nssnoc_memnoc_bfdcd_clk_src[] = { F(533333333, P_GPLL0, 1.5, 0, 0), { } @@ -4037,14 +4149,17 @@ static struct clk_regmap *gcc_ipq9574_clks[] = { [WCSS_AHB_CLK_SRC] = &wcss_ahb_clk_src.clkr, [GCC_Q6_AHB_CLK] = &gcc_q6_ahb_clk.clkr, [GCC_Q6_AHB_S_CLK] = &gcc_q6_ahb_s_clk.clkr, + [GCC_WCSS_AHB_S_CLK] = &gcc_wcss_ahb_s_clk.clkr, [GCC_WCSS_ECAHB_CLK] = &gcc_wcss_ecahb_clk.clkr, [GCC_WCSS_ACMT_CLK] = &gcc_wcss_acmt_clk.clkr, [GCC_SYS_NOC_WCSS_AHB_CLK] = &gcc_sys_noc_wcss_ahb_clk.clkr, [WCSS_AXI_M_CLK_SRC] = &wcss_axi_m_clk_src.clkr, + [GCC_WCSS_AXI_M_CLK] = &gcc_wcss_axi_m_clk.clkr, [GCC_ANOC_WCSS_AXI_M_CLK] = &gcc_anoc_wcss_axi_m_clk.clkr, [QDSS_AT_CLK_SRC] = &qdss_at_clk_src.clkr, [GCC_Q6SS_ATBM_CLK] = &gcc_q6ss_atbm_clk.clkr, [GCC_WCSS_DBG_IFC_ATB_CLK] = &gcc_wcss_dbg_ifc_atb_clk.clkr, + [GCC_WCSS_DBG_IFC_ATB_BDG_CLK] = &gcc_wcss_dbg_ifc_atb_bdg_clk.clkr, [GCC_NSSNOC_ATB_CLK] = &gcc_nssnoc_atb_clk.clkr, [GCC_QDSS_AT_CLK] = &gcc_qdss_at_clk.clkr, [GCC_SYS_NOC_AT_CLK] = &gcc_sys_noc_at_clk.clkr, @@ -4059,6 +4174,7 @@ static struct clk_regmap *gcc_ipq9574_clks[] = { [QDSS_TSCTR_CLK_SRC] = &qdss_tsctr_clk_src.clkr, [GCC_Q6_TSCTR_1TO2_CLK] = &gcc_q6_tsctr_1to2_clk.clkr, [GCC_WCSS_DBG_IFC_NTS_CLK] = &gcc_wcss_dbg_ifc_nts_clk.clkr, + [GCC_WCSS_DBG_IFC_NTS_BDG_CLK] = &gcc_wcss_dbg_ifc_nts_bdg_clk.clkr, [GCC_QDSS_TSCTR_DIV2_CLK] = &gcc_qdss_tsctr_div2_clk.clkr, [GCC_QDSS_TS_CLK] = &gcc_qdss_ts_clk.clkr, [GCC_QDSS_TSCTR_DIV4_CLK] = &gcc_qdss_tsctr_div4_clk.clkr, @@ -4068,7 +4184,9 @@ static struct clk_regmap *gcc_ipq9574_clks[] = { [GCC_Q6SS_PCLKDBG_CLK] = &gcc_q6ss_pclkdbg_clk.clkr, [GCC_Q6SS_TRIG_CLK] = &gcc_q6ss_trig_clk.clkr, [GCC_WCSS_DBG_IFC_APB_CLK] = &gcc_wcss_dbg_ifc_apb_clk.clkr, + [GCC_WCSS_DBG_IFC_APB_BDG_CLK] = &gcc_wcss_dbg_ifc_apb_bdg_clk.clkr, [GCC_WCSS_DBG_IFC_DAPBUS_CLK] = &gcc_wcss_dbg_ifc_dapbus_clk.clkr, + [GCC_WCSS_DBG_IFC_DAPBUS_BDG_CLK] = &gcc_wcss_dbg_ifc_dapbus_bdg_clk.clkr, [GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr, [GCC_QDSS_APB2JTAG_CLK] = &gcc_qdss_apb2jtag_clk.clkr, [GCC_QDSS_TSCTR_DIV3_CLK] = &gcc_qdss_tsctr_div3_clk.clkr, @@ -4076,6 +4194,7 @@ static struct clk_regmap *gcc_ipq9574_clks[] = { [GCC_QPIC_IO_MACRO_CLK] = &gcc_qpic_io_macro_clk.clkr, [Q6_AXI_CLK_SRC] = &q6_axi_clk_src.clkr, [GCC_Q6_AXIM_CLK] = &gcc_q6_axim_clk.clkr, + [GCC_Q6_AXIM2_CLK] = &gcc_q6_axim2_clk.clkr, [GCC_WCSS_Q6_TBU_CLK] = &gcc_wcss_q6_tbu_clk.clkr, [GCC_MEM_NOC_Q6_AXI_CLK] = &gcc_mem_noc_q6_axi_clk.clkr, [Q6_AXIM2_CLK_SRC] = &q6_axim2_clk_src.clkr,
Some of the clocks required for q6/wcss bring up are missing. So this patch adds clocks. Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com> --- drivers/clk/qcom/gcc-ipq9574.c | 119 +++++++++++++++++++++++++++++++++ 1 file changed, 119 insertions(+)