| Message ID | 20230510223552.89656-2-radhakrishna.sripada@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [1/2] drm/i915/mtl: Extend Wa_16014892111 to MTL | expand |
Quoting Radhakrishna Sripada (2023-05-10 19:35:52) >MTL reuses the tuning parameters for DG2. Extend the dg2 >performance tuning parameters to MTL. > >Bspec: 68331 >Cc: Matt Roper <matthew.d.roper@intel.com> >Cc: Gustavo Sousa <gustavo.sousa@intel.com> >Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Commit cebc13de7e70 ("drm/i915: Whitelist COMMON_SLICE_CHICKEN3 for UMD access") already whitelisted one of the registers supposed to be tweaked by UMD and I did check that all remaining registers from the performance tuning list are now covered by this patch. Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com> >--- > drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 ++++-- > 1 file changed, 4 insertions(+), 2 deletions(-) > >diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c >index 786349e95487..b222a3d367c9 100644 >--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c >+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c >@@ -817,6 +817,8 @@ static void mtl_ctx_workarounds_init(struct intel_engine_cs *engine, > { > struct drm_i915_private *i915 = engine->i915; > >+ dg2_ctx_gt_tuning_init(engine, wal); >+ > if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) || > IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) { > /* Wa_14014947963 */ >@@ -1754,7 +1756,7 @@ static void gt_tuning_settings(struct intel_gt *gt, struct i915_wa_list *wal) > wa_mcr_masked_en(wal, XEHPC_LNCFMISCCFGREG0, XEHPC_HOSTCACHEEN); > } > >- if (IS_DG2(gt->i915)) { >+ if (IS_DG2(gt->i915) || IS_METEORLAKE(gt->i915)) { > wa_mcr_write_or(wal, XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS); > wa_mcr_write_or(wal, XEHP_SQCM, EN_32B_ACCESS); > } >@@ -2944,7 +2946,7 @@ static void > add_render_compute_tuning_settings(struct drm_i915_private *i915, > struct i915_wa_list *wal) > { >- if (IS_DG2(i915)) >+ if (IS_DG2(i915) || IS_METEORLAKE(i915)) > wa_mcr_write_clr_set(wal, RT_CTRL, STACKID_CTRL, STACKID_CTRL_512); > > /* >-- >2.34.1 >
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 786349e95487..b222a3d367c9 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -817,6 +817,8 @@ static void mtl_ctx_workarounds_init(struct intel_engine_cs *engine, { struct drm_i915_private *i915 = engine->i915; + dg2_ctx_gt_tuning_init(engine, wal); + if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) || IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) { /* Wa_14014947963 */ @@ -1754,7 +1756,7 @@ static void gt_tuning_settings(struct intel_gt *gt, struct i915_wa_list *wal) wa_mcr_masked_en(wal, XEHPC_LNCFMISCCFGREG0, XEHPC_HOSTCACHEEN); } - if (IS_DG2(gt->i915)) { + if (IS_DG2(gt->i915) || IS_METEORLAKE(gt->i915)) { wa_mcr_write_or(wal, XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS); wa_mcr_write_or(wal, XEHP_SQCM, EN_32B_ACCESS); } @@ -2944,7 +2946,7 @@ static void add_render_compute_tuning_settings(struct drm_i915_private *i915, struct i915_wa_list *wal) { - if (IS_DG2(i915)) + if (IS_DG2(i915) || IS_METEORLAKE(i915)) wa_mcr_write_clr_set(wal, RT_CTRL, STACKID_CTRL, STACKID_CTRL_512); /*
MTL reuses the tuning parameters for DG2. Extend the dg2 performance tuning parameters to MTL. Bspec: 68331 Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Gustavo Sousa <gustavo.sousa@intel.com> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-)