| Message ID | 20230511150539.3.I525a2ed4260046d43c885ee1275e91707743df1c@changeid (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | irqchip/gic-v3: Disable pseudo NMIs on Mediatek Chromebooks w/ bad FW | expand |
Reviewed-by: Julius Werner <jwerner@chromium.org>
On Thu, 11 May 2023 23:05:37 +0100, Douglas Anderson <dianders@chromium.org> wrote: > > Firmware shipped on mt8183 Chromebooks is affected by the GICR > save/restore issue as described by the patch ("dt-bindings: > interrupt-controller: arm,gic-v3: Add quirk for Mediatek SoCs w/ > broken FW"). Add the quirk property. > > Fixes: e526c9bc11f8 ("arm64: dts: Add Mediatek SoC MT8183 and evaluation board dts and Makefile") > Signed-off-by: Douglas Anderson <dianders@chromium.org> > --- > > arch/arm64/boot/dts/mediatek/mt8183.dtsi | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi > index 5169779d01df..39545172fce5 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi > @@ -709,6 +709,7 @@ gic: interrupt-controller@c000000 { > <0 0x0c400000 0 0x2000>, /* GICC */ > <0 0x0c410000 0 0x1000>, /* GICH */ > <0 0x0c420000 0 0x2000>; /* GICV */ > + mediatek,gicr-save-quirk; Is that something you can safely generalise at the SoC level? Are these SoC solely used on Chromebooks, and/or without any hope of seeing any alternative FW being already in use? M.
Hi, On Fri, May 12, 2023 at 1:13 AM Marc Zyngier <maz@kernel.org> wrote: > > On Thu, 11 May 2023 23:05:37 +0100, > Douglas Anderson <dianders@chromium.org> wrote: > > > > Firmware shipped on mt8183 Chromebooks is affected by the GICR > > save/restore issue as described by the patch ("dt-bindings: > > interrupt-controller: arm,gic-v3: Add quirk for Mediatek SoCs w/ > > broken FW"). Add the quirk property. > > > > Fixes: e526c9bc11f8 ("arm64: dts: Add Mediatek SoC MT8183 and evaluation board dts and Makefile") > > Signed-off-by: Douglas Anderson <dianders@chromium.org> > > --- > > > > arch/arm64/boot/dts/mediatek/mt8183.dtsi | 1 + > > 1 file changed, 1 insertion(+) > > > > diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi > > index 5169779d01df..39545172fce5 100644 > > --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi > > +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi > > @@ -709,6 +709,7 @@ gic: interrupt-controller@c000000 { > > <0 0x0c400000 0 0x2000>, /* GICC */ > > <0 0x0c410000 0 0x1000>, /* GICH */ > > <0 0x0c420000 0 0x2000>; /* GICV */ > > + mediatek,gicr-save-quirk; > > Is that something you can safely generalise at the SoC level? Are > these SoC solely used on Chromebooks, and/or Hmmm, I thought I checked to make sure that the only users of these upstream were Chromebooks, but I just double-checked and I obviously was blind yesterday. You're right that I need to fix this. I will move these to: mt8195-cherry.dtsi mt8192-asurada.dtsi mt8183-kukui.dtsi ...it looks as if the common "baseboard" dtsi for mt8186 Chromebooks hasn't been upstreamed yet, so we'll have to keep an eye on that and make sure it gets the property. When I spin this series early next week I'll make that change. > without any hope of > seeing any alternative FW being already in use? I haven't seen anyone try to fully replace the firmware of a Chromebook in the past. It would be a lot of work, certainly. More common, I'd think, would be someone chaining an extra level of loader between the existing firmware and the OS. I _think_ I've seen people use a stripped down U-Boot for this. However, the "resident" firmware would still be the one that the Chromebook ships with. Certainly someone could prove me wrong and re-implement the firmware on one of these Chromebooks. That person would need to follow the same convention or accept that their kernel won't be enabling pseudoNMIs. -Doug
Il 12/05/23 00:05, Douglas Anderson ha scritto: > Firmware shipped on mt8183 Chromebooks is affected by the GICR > save/restore issue as described by the patch ("dt-bindings: > interrupt-controller: arm,gic-v3: Add quirk for Mediatek SoCs w/ > broken FW"). Add the quirk property. > > Fixes: e526c9bc11f8 ("arm64: dts: Add Mediatek SoC MT8183 and evaluation board dts and Makefile") > Signed-off-by: Douglas Anderson <dianders@chromium.org> > --- > > arch/arm64/boot/dts/mediatek/mt8183.dtsi | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi > index 5169779d01df..39545172fce5 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi > @@ -709,6 +709,7 @@ gic: interrupt-controller@c000000 { > <0 0x0c400000 0 0x2000>, /* GICC */ > <0 0x0c410000 0 0x1000>, /* GICH */ > <0 0x0c420000 0 0x2000>; /* GICV */ > + mediatek,gicr-save-quirk; Nit: Can you please move this after interrupts? Thanks, Angelo > > interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; > ppi-partitions {
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index 5169779d01df..39545172fce5 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -709,6 +709,7 @@ gic: interrupt-controller@c000000 { <0 0x0c400000 0 0x2000>, /* GICC */ <0 0x0c410000 0 0x1000>, /* GICH */ <0 0x0c420000 0 0x2000>; /* GICV */ + mediatek,gicr-save-quirk; interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; ppi-partitions {
Firmware shipped on mt8183 Chromebooks is affected by the GICR save/restore issue as described by the patch ("dt-bindings: interrupt-controller: arm,gic-v3: Add quirk for Mediatek SoCs w/ broken FW"). Add the quirk property. Fixes: e526c9bc11f8 ("arm64: dts: Add Mediatek SoC MT8183 and evaluation board dts and Makefile") Signed-off-by: Douglas Anderson <dianders@chromium.org> --- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 1 + 1 file changed, 1 insertion(+)