| Message ID | 20230512022036.97987-4-xingyu.wu@starfivetech.com (mailing list archive) |
|---|---|
| State | Changes Requested, archived |
| Headers | show |
| Series | Add PLL clocks driver and syscon for StarFive JH7110 SoC | expand |
On Fri, May 12, 2023 at 10:20:32AM +0800, Xingyu Wu wrote: > Add PLL clock inputs from PLL clock generator. > > Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> > --- > .../clock/starfive,jh7110-syscrg.yaml | 20 +++++++++++++++++-- > 1 file changed, 18 insertions(+), 2 deletions(-) /tmp/tmp.KDlzwQM5ma/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.3b.dtb: clock-controller@13020000: clocks: 'oneOf' conditional failed, one must be fixed: [[19], [20], [21], [22], [23], [24], [25], [26], [27]] is too short From schema: /Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml /tmp/tmp.KDlzwQM5ma/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.3b.dtb: clock-controller@13020000: clock-names: 'oneOf' conditional failed, one must be fixed: ['osc', 'gmac1_rmii_refin', 'gmac1_rgmii_rxin', 'i2stx_bclk_ext', 'i2stx_lrck_ext', 'i2srx_bclk_ext', 'i2srx_lrck_ext', 'tdm_ext', 'mclk_ext'] is too short 'i2stx_bclk_ext' was expected 'i2stx_lrck_ext' was expected 'i2srx_bclk_ext' was expected 'i2srx_lrck_ext' was expected 'tdm_ext' was expected 'mclk_ext' was expected 'pll0_out' was expected From schema: /Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml /tmp/tmp.KDlzwQM5ma/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.2a.dtb: clock-controller@13020000: clocks: 'oneOf' conditional failed, one must be fixed: [[19], [20], [21], [22], [23], [24], [25], [26], [27]] is too short From schema: Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml /tmp/tmp.KDlzwQM5ma/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.2a.dtb: clock-controller@13020000: clock-names: 'oneOf' conditional failed, one must be fixed: ['osc', 'gmac1_rmii_refin', 'gmac1_rgmii_rxin', 'i2stx_bclk_ext', 'i2stx_lrck_ext', 'i2srx_bclk_ext', 'i2srx_lrck_ext', 'tdm_ext', 'mclk_ext'] is too short 'i2stx_bclk_ext' was expected 'i2stx_lrck_ext' was expected 'i2srx_bclk_ext' was expected 'i2srx_lrck_ext' was expected 'tdm_ext' was expected 'mclk_ext' was expected 'pll0_out' was expected Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml This binding change is incompatible with the existing devicetrees for the visionfive 2.
On 2023/5/12 14:47, Conor Dooley wrote: > On Fri, May 12, 2023 at 10:20:32AM +0800, Xingyu Wu wrote: >> Add PLL clock inputs from PLL clock generator. >> >> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> >> Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> >> --- >> .../clock/starfive,jh7110-syscrg.yaml | 20 +++++++++++++++++-- >> 1 file changed, 18 insertions(+), 2 deletions(-) > > /tmp/tmp.KDlzwQM5ma/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.3b.dtb: clock-controller@13020000: clocks: 'oneOf' conditional failed, one must be fixed: > [[19], [20], [21], [22], [23], [24], [25], [26], [27]] is too short > From schema: /Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml > /tmp/tmp.KDlzwQM5ma/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.3b.dtb: clock-controller@13020000: clock-names: 'oneOf' conditional failed, one must be fixed: > ['osc', 'gmac1_rmii_refin', 'gmac1_rgmii_rxin', 'i2stx_bclk_ext', 'i2stx_lrck_ext', 'i2srx_bclk_ext', 'i2srx_lrck_ext', 'tdm_ext', 'mclk_ext'] is too short > 'i2stx_bclk_ext' was expected > 'i2stx_lrck_ext' was expected > 'i2srx_bclk_ext' was expected > 'i2srx_lrck_ext' was expected > 'tdm_ext' was expected > 'mclk_ext' was expected > 'pll0_out' was expected > From schema: /Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml > /tmp/tmp.KDlzwQM5ma/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.2a.dtb: clock-controller@13020000: clocks: 'oneOf' conditional failed, one must be fixed: > [[19], [20], [21], [22], [23], [24], [25], [26], [27]] is too short > From schema: Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml > /tmp/tmp.KDlzwQM5ma/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.2a.dtb: clock-controller@13020000: clock-names: 'oneOf' conditional failed, one must be fixed: > ['osc', 'gmac1_rmii_refin', 'gmac1_rgmii_rxin', 'i2stx_bclk_ext', 'i2stx_lrck_ext', 'i2srx_bclk_ext', 'i2srx_lrck_ext', 'tdm_ext', 'mclk_ext'] is too short > 'i2stx_bclk_ext' was expected > 'i2stx_lrck_ext' was expected > 'i2srx_bclk_ext' was expected > 'i2srx_lrck_ext' was expected > 'tdm_ext' was expected > 'mclk_ext' was expected > 'pll0_out' was expected > Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml > > This binding change is incompatible with the existing devicetrees for > the visionfive 2. This looks like less clocks about PLL in SYSCRG node. And I add this in patch 7. Best regards, Xingyu Wu
On Fri, May 12, 2023 at 04:07:47PM +0800, Xingyu Wu wrote: > On 2023/5/12 14:47, Conor Dooley wrote: > > On Fri, May 12, 2023 at 10:20:32AM +0800, Xingyu Wu wrote: > >> Add PLL clock inputs from PLL clock generator. > >> > >> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > >> Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> > >> --- > >> .../clock/starfive,jh7110-syscrg.yaml | 20 +++++++++++++++++-- > >> 1 file changed, 18 insertions(+), 2 deletions(-) > > > > /tmp/tmp.KDlzwQM5ma/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.3b.dtb: clock-controller@13020000: clocks: 'oneOf' conditional failed, one must be fixed: > > [[19], [20], [21], [22], [23], [24], [25], [26], [27]] is too short > > From schema: /Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml > > /tmp/tmp.KDlzwQM5ma/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.3b.dtb: clock-controller@13020000: clock-names: 'oneOf' conditional failed, one must be fixed: > > ['osc', 'gmac1_rmii_refin', 'gmac1_rgmii_rxin', 'i2stx_bclk_ext', 'i2stx_lrck_ext', 'i2srx_bclk_ext', 'i2srx_lrck_ext', 'tdm_ext', 'mclk_ext'] is too short > > 'i2stx_bclk_ext' was expected > > 'i2stx_lrck_ext' was expected > > 'i2srx_bclk_ext' was expected > > 'i2srx_lrck_ext' was expected > > 'tdm_ext' was expected > > 'mclk_ext' was expected > > 'pll0_out' was expected > > From schema: /Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml > > /tmp/tmp.KDlzwQM5ma/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.2a.dtb: clock-controller@13020000: clocks: 'oneOf' conditional failed, one must be fixed: > > [[19], [20], [21], [22], [23], [24], [25], [26], [27]] is too short > > From schema: Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml > > /tmp/tmp.KDlzwQM5ma/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.2a.dtb: clock-controller@13020000: clock-names: 'oneOf' conditional failed, one must be fixed: > > ['osc', 'gmac1_rmii_refin', 'gmac1_rgmii_rxin', 'i2stx_bclk_ext', 'i2stx_lrck_ext', 'i2srx_bclk_ext', 'i2srx_lrck_ext', 'tdm_ext', 'mclk_ext'] is too short > > 'i2stx_bclk_ext' was expected > > 'i2stx_lrck_ext' was expected > > 'i2srx_bclk_ext' was expected > > 'i2srx_lrck_ext' was expected > > 'tdm_ext' was expected > > 'mclk_ext' was expected > > 'pll0_out' was expected > > Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml > > > > This binding change is incompatible with the existing devicetrees for > > the visionfive 2. > > This looks like less clocks about PLL in SYSCRG node. And I add this in patch 7. The existing devicetree is a valid, albeit limited, description of the hardware. After your changes to the clock driver in this series, but *without* the changes to the devicetrees, does the system still function? From a quick check of 4/7, it looks like it will not?
On 2023/5/12 17:35, Conor Dooley wrote: > On Fri, May 12, 2023 at 04:07:47PM +0800, Xingyu Wu wrote: >> On 2023/5/12 14:47, Conor Dooley wrote: >> > On Fri, May 12, 2023 at 10:20:32AM +0800, Xingyu Wu wrote: >> >> Add PLL clock inputs from PLL clock generator. >> >> >> >> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> >> >> Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> >> >> --- >> >> .../clock/starfive,jh7110-syscrg.yaml | 20 +++++++++++++++++-- >> >> 1 file changed, 18 insertions(+), 2 deletions(-) >> > >> > /tmp/tmp.KDlzwQM5ma/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.3b.dtb: clock-controller@13020000: clocks: 'oneOf' conditional failed, one must be fixed: >> > [[19], [20], [21], [22], [23], [24], [25], [26], [27]] is too short >> > From schema: /Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml >> > /tmp/tmp.KDlzwQM5ma/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.3b.dtb: clock-controller@13020000: clock-names: 'oneOf' conditional failed, one must be fixed: >> > ['osc', 'gmac1_rmii_refin', 'gmac1_rgmii_rxin', 'i2stx_bclk_ext', 'i2stx_lrck_ext', 'i2srx_bclk_ext', 'i2srx_lrck_ext', 'tdm_ext', 'mclk_ext'] is too short >> > 'i2stx_bclk_ext' was expected >> > 'i2stx_lrck_ext' was expected >> > 'i2srx_bclk_ext' was expected >> > 'i2srx_lrck_ext' was expected >> > 'tdm_ext' was expected >> > 'mclk_ext' was expected >> > 'pll0_out' was expected >> > From schema: /Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml >> > /tmp/tmp.KDlzwQM5ma/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.2a.dtb: clock-controller@13020000: clocks: 'oneOf' conditional failed, one must be fixed: >> > [[19], [20], [21], [22], [23], [24], [25], [26], [27]] is too short >> > From schema: Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml >> > /tmp/tmp.KDlzwQM5ma/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.2a.dtb: clock-controller@13020000: clock-names: 'oneOf' conditional failed, one must be fixed: >> > ['osc', 'gmac1_rmii_refin', 'gmac1_rgmii_rxin', 'i2stx_bclk_ext', 'i2stx_lrck_ext', 'i2srx_bclk_ext', 'i2srx_lrck_ext', 'tdm_ext', 'mclk_ext'] is too short >> > 'i2stx_bclk_ext' was expected >> > 'i2stx_lrck_ext' was expected >> > 'i2srx_bclk_ext' was expected >> > 'i2srx_lrck_ext' was expected >> > 'tdm_ext' was expected >> > 'mclk_ext' was expected >> > 'pll0_out' was expected >> > Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml >> > >> > This binding change is incompatible with the existing devicetrees for >> > the visionfive 2. >> >> This looks like less clocks about PLL in SYSCRG node. And I add this in patch 7. > > The existing devicetree is a valid, albeit limited, description of the > hardware. > After your changes to the clock driver in this series, but *without* the > changes to the devicetrees, does the system still function? > From a quick check of 4/7, it looks like it will not? I just tested it on the board and the system still worked without the changes about devicetree. But these clocks' rate were 0 because these could not get the PLL clocks from devicetree. Best regards, Xingyu Wu
On Fri, May 12, 2023 at 05:56:16PM +0800, Xingyu Wu wrote: > On 2023/5/12 17:35, Conor Dooley wrote: > > On Fri, May 12, 2023 at 04:07:47PM +0800, Xingyu Wu wrote: > >> On 2023/5/12 14:47, Conor Dooley wrote: > >> > On Fri, May 12, 2023 at 10:20:32AM +0800, Xingyu Wu wrote: > >> >> Add PLL clock inputs from PLL clock generator. > >> >> > >> >> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > >> >> Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> > >> >> --- > >> >> .../clock/starfive,jh7110-syscrg.yaml | 20 +++++++++++++++++-- > >> >> 1 file changed, 18 insertions(+), 2 deletions(-) > >> > > >> > /tmp/tmp.KDlzwQM5ma/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.3b.dtb: clock-controller@13020000: clocks: 'oneOf' conditional failed, one must be fixed: > >> > [[19], [20], [21], [22], [23], [24], [25], [26], [27]] is too short > >> > From schema: /Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml > >> > /tmp/tmp.KDlzwQM5ma/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.3b.dtb: clock-controller@13020000: clock-names: 'oneOf' conditional failed, one must be fixed: > >> > ['osc', 'gmac1_rmii_refin', 'gmac1_rgmii_rxin', 'i2stx_bclk_ext', 'i2stx_lrck_ext', 'i2srx_bclk_ext', 'i2srx_lrck_ext', 'tdm_ext', 'mclk_ext'] is too short > >> > 'i2stx_bclk_ext' was expected > >> > 'i2stx_lrck_ext' was expected > >> > 'i2srx_bclk_ext' was expected > >> > 'i2srx_lrck_ext' was expected > >> > 'tdm_ext' was expected > >> > 'mclk_ext' was expected > >> > 'pll0_out' was expected > >> > From schema: /Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml > >> > /tmp/tmp.KDlzwQM5ma/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.2a.dtb: clock-controller@13020000: clocks: 'oneOf' conditional failed, one must be fixed: > >> > [[19], [20], [21], [22], [23], [24], [25], [26], [27]] is too short > >> > From schema: Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml > >> > /tmp/tmp.KDlzwQM5ma/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.2a.dtb: clock-controller@13020000: clock-names: 'oneOf' conditional failed, one must be fixed: > >> > ['osc', 'gmac1_rmii_refin', 'gmac1_rgmii_rxin', 'i2stx_bclk_ext', 'i2stx_lrck_ext', 'i2srx_bclk_ext', 'i2srx_lrck_ext', 'tdm_ext', 'mclk_ext'] is too short > >> > 'i2stx_bclk_ext' was expected > >> > 'i2stx_lrck_ext' was expected > >> > 'i2srx_bclk_ext' was expected > >> > 'i2srx_lrck_ext' was expected > >> > 'tdm_ext' was expected > >> > 'mclk_ext' was expected > >> > 'pll0_out' was expected > >> > Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml > >> > > >> > This binding change is incompatible with the existing devicetrees for > >> > the visionfive 2. > >> > >> This looks like less clocks about PLL in SYSCRG node. And I add this in patch 7. > > > > The existing devicetree is a valid, albeit limited, description of the > > hardware. > > After your changes to the clock driver in this series, but *without* the > > changes to the devicetrees, does the system still function? > > From a quick check of 4/7, it looks like it will not? > > I just tested it on the board and the system still worked without the changes > about devicetree. But these clocks' rate were 0 because these could not get > the PLL clocks from devicetree. Hmm, that sounds like an issue to me. If all of the clock rates are computed based off of parents that incorrectly report 0, are we not in for trouble? Should the fixed-factor clocks be retained as a fallback for the sake of compatibility? Emil, Stephen?
On 2023/5/12 21:49, Conor Dooley wrote: > On Fri, May 12, 2023 at 05:56:16PM +0800, Xingyu Wu wrote: >> On 2023/5/12 17:35, Conor Dooley wrote: >> > On Fri, May 12, 2023 at 04:07:47PM +0800, Xingyu Wu wrote: >> >> On 2023/5/12 14:47, Conor Dooley wrote: >> >> > On Fri, May 12, 2023 at 10:20:32AM +0800, Xingyu Wu wrote: >> >> >> Add PLL clock inputs from PLL clock generator. >> >> >> >> >> >> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> >> >> >> Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> >> >> >> --- >> >> >> .../clock/starfive,jh7110-syscrg.yaml | 20 +++++++++++++++++-- >> >> >> 1 file changed, 18 insertions(+), 2 deletions(-) >> >> > >> >> > /tmp/tmp.KDlzwQM5ma/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.3b.dtb: clock-controller@13020000: clocks: 'oneOf' conditional failed, one must be fixed: >> >> > [[19], [20], [21], [22], [23], [24], [25], [26], [27]] is too short >> >> > From schema: /Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml >> >> > /tmp/tmp.KDlzwQM5ma/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.3b.dtb: clock-controller@13020000: clock-names: 'oneOf' conditional failed, one must be fixed: >> >> > ['osc', 'gmac1_rmii_refin', 'gmac1_rgmii_rxin', 'i2stx_bclk_ext', 'i2stx_lrck_ext', 'i2srx_bclk_ext', 'i2srx_lrck_ext', 'tdm_ext', 'mclk_ext'] is too short >> >> > 'i2stx_bclk_ext' was expected >> >> > 'i2stx_lrck_ext' was expected >> >> > 'i2srx_bclk_ext' was expected >> >> > 'i2srx_lrck_ext' was expected >> >> > 'tdm_ext' was expected >> >> > 'mclk_ext' was expected >> >> > 'pll0_out' was expected >> >> > From schema: /Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml >> >> > /tmp/tmp.KDlzwQM5ma/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.2a.dtb: clock-controller@13020000: clocks: 'oneOf' conditional failed, one must be fixed: >> >> > [[19], [20], [21], [22], [23], [24], [25], [26], [27]] is too short >> >> > From schema: Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml >> >> > /tmp/tmp.KDlzwQM5ma/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.2a.dtb: clock-controller@13020000: clock-names: 'oneOf' conditional failed, one must be fixed: >> >> > ['osc', 'gmac1_rmii_refin', 'gmac1_rgmii_rxin', 'i2stx_bclk_ext', 'i2stx_lrck_ext', 'i2srx_bclk_ext', 'i2srx_lrck_ext', 'tdm_ext', 'mclk_ext'] is too short >> >> > 'i2stx_bclk_ext' was expected >> >> > 'i2stx_lrck_ext' was expected >> >> > 'i2srx_bclk_ext' was expected >> >> > 'i2srx_lrck_ext' was expected >> >> > 'tdm_ext' was expected >> >> > 'mclk_ext' was expected >> >> > 'pll0_out' was expected >> >> > Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml >> >> > >> >> > This binding change is incompatible with the existing devicetrees for >> >> > the visionfive 2. >> >> >> >> This looks like less clocks about PLL in SYSCRG node. And I add this in patch 7. >> > >> > The existing devicetree is a valid, albeit limited, description of the >> > hardware. >> > After your changes to the clock driver in this series, but *without* the >> > changes to the devicetrees, does the system still function? >> > From a quick check of 4/7, it looks like it will not? >> >> I just tested it on the board and the system still worked without the changes >> about devicetree. But these clocks' rate were 0 because these could not get >> the PLL clocks from devicetree. > > Hmm, that sounds like an issue to me. If all of the clock rates are > computed based off of parents that incorrectly report 0, are we not in > for trouble? > Should the fixed-factor clocks be retained as a fallback for the sake of > compatibility? > Emil, Stephen? I got your concern. Actually, I can add a check in driver to see if the dts has pll clocks and then decide whether to use fixed-factor clocks or pll clocks from syscon. But eventually we have to use pll clocks and dts has to add it. Then the binding should add it synchronously, right? Best regards, Xingyu Wu
On Fri, May 19, 2023 at 03:59:19PM +0800, Xingyu Wu wrote: > On 2023/5/12 21:49, Conor Dooley wrote: > > On Fri, May 12, 2023 at 05:56:16PM +0800, Xingyu Wu wrote: > >> On 2023/5/12 17:35, Conor Dooley wrote: > >> > On Fri, May 12, 2023 at 04:07:47PM +0800, Xingyu Wu wrote: > >> >> On 2023/5/12 14:47, Conor Dooley wrote: > >> >> > On Fri, May 12, 2023 at 10:20:32AM +0800, Xingyu Wu wrote: > >> >> >> Add PLL clock inputs from PLL clock generator. > >> >> >> > >> >> >> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > >> >> >> Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> > >> >> >> --- > >> >> >> .../clock/starfive,jh7110-syscrg.yaml | 20 +++++++++++++++++-- > >> >> >> 1 file changed, 18 insertions(+), 2 deletions(-) > >> >> > > >> >> > /tmp/tmp.KDlzwQM5ma/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.3b.dtb: clock-controller@13020000: clocks: 'oneOf' conditional failed, one must be fixed: > >> >> > [[19], [20], [21], [22], [23], [24], [25], [26], [27]] is too short > >> >> > From schema: /Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml > >> >> > /tmp/tmp.KDlzwQM5ma/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.3b.dtb: clock-controller@13020000: clock-names: 'oneOf' conditional failed, one must be fixed: > >> >> > ['osc', 'gmac1_rmii_refin', 'gmac1_rgmii_rxin', 'i2stx_bclk_ext', 'i2stx_lrck_ext', 'i2srx_bclk_ext', 'i2srx_lrck_ext', 'tdm_ext', 'mclk_ext'] is too short > >> >> > 'i2stx_bclk_ext' was expected > >> >> > 'i2stx_lrck_ext' was expected > >> >> > 'i2srx_bclk_ext' was expected > >> >> > 'i2srx_lrck_ext' was expected > >> >> > 'tdm_ext' was expected > >> >> > 'mclk_ext' was expected > >> >> > 'pll0_out' was expected > >> >> > From schema: /Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml > >> >> > /tmp/tmp.KDlzwQM5ma/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.2a.dtb: clock-controller@13020000: clocks: 'oneOf' conditional failed, one must be fixed: > >> >> > [[19], [20], [21], [22], [23], [24], [25], [26], [27]] is too short > >> >> > From schema: Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml > >> >> > /tmp/tmp.KDlzwQM5ma/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.2a.dtb: clock-controller@13020000: clock-names: 'oneOf' conditional failed, one must be fixed: > >> >> > ['osc', 'gmac1_rmii_refin', 'gmac1_rgmii_rxin', 'i2stx_bclk_ext', 'i2stx_lrck_ext', 'i2srx_bclk_ext', 'i2srx_lrck_ext', 'tdm_ext', 'mclk_ext'] is too short > >> >> > 'i2stx_bclk_ext' was expected > >> >> > 'i2stx_lrck_ext' was expected > >> >> > 'i2srx_bclk_ext' was expected > >> >> > 'i2srx_lrck_ext' was expected > >> >> > 'tdm_ext' was expected > >> >> > 'mclk_ext' was expected > >> >> > 'pll0_out' was expected > >> >> > Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml > >> >> > > >> >> > This binding change is incompatible with the existing devicetrees for > >> >> > the visionfive 2. > >> >> > >> >> This looks like less clocks about PLL in SYSCRG node. And I add this in patch 7. > >> > > >> > The existing devicetree is a valid, albeit limited, description of the > >> > hardware. > >> > After your changes to the clock driver in this series, but *without* the > >> > changes to the devicetrees, does the system still function? > >> > From a quick check of 4/7, it looks like it will not? > >> > >> I just tested it on the board and the system still worked without the changes > >> about devicetree. But these clocks' rate were 0 because these could not get > >> the PLL clocks from devicetree. > > > > Hmm, that sounds like an issue to me. If all of the clock rates are > > computed based off of parents that incorrectly report 0, are we not in > > for trouble? > > Should the fixed-factor clocks be retained as a fallback for the sake of > > compatibility? > > Emil, Stephen? > > I got your concern. Actually, I can add a check in driver to see if the dts > has pll clocks and then decide whether to use fixed-factor clocks or pll clocks > from syscon. But eventually we have to use pll clocks and dts has to add it. > Then the binding should add it synchronously, right? IMO, it is okay to change the bindings to only allow the "correct" representation of the clock tree, but the driver should fall back to the fixed factor clocks if it detects the old/limited configuration. Cheers, Conor.
On 2023/5/19 16:12, Conor Dooley wrote: > On Fri, May 19, 2023 at 03:59:19PM +0800, Xingyu Wu wrote: >> On 2023/5/12 21:49, Conor Dooley wrote: >> > On Fri, May 12, 2023 at 05:56:16PM +0800, Xingyu Wu wrote: >> >> On 2023/5/12 17:35, Conor Dooley wrote: >> >> > On Fri, May 12, 2023 at 04:07:47PM +0800, Xingyu Wu wrote: >> >> >> On 2023/5/12 14:47, Conor Dooley wrote: >> >> >> > On Fri, May 12, 2023 at 10:20:32AM +0800, Xingyu Wu wrote: >> >> >> >> Add PLL clock inputs from PLL clock generator. >> >> >> >> >> >> >> >> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> >> >> >> >> Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> >> >> >> >> --- >> >> >> >> .../clock/starfive,jh7110-syscrg.yaml | 20 +++++++++++++++++-- >> >> >> >> 1 file changed, 18 insertions(+), 2 deletions(-) >> >> >> > >> >> >> > /tmp/tmp.KDlzwQM5ma/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.3b.dtb: clock-controller@13020000: clocks: 'oneOf' conditional failed, one must be fixed: >> >> >> > [[19], [20], [21], [22], [23], [24], [25], [26], [27]] is too short >> >> >> > From schema: /Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml >> >> >> > /tmp/tmp.KDlzwQM5ma/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.3b.dtb: clock-controller@13020000: clock-names: 'oneOf' conditional failed, one must be fixed: >> >> >> > ['osc', 'gmac1_rmii_refin', 'gmac1_rgmii_rxin', 'i2stx_bclk_ext', 'i2stx_lrck_ext', 'i2srx_bclk_ext', 'i2srx_lrck_ext', 'tdm_ext', 'mclk_ext'] is too short >> >> >> > 'i2stx_bclk_ext' was expected >> >> >> > 'i2stx_lrck_ext' was expected >> >> >> > 'i2srx_bclk_ext' was expected >> >> >> > 'i2srx_lrck_ext' was expected >> >> >> > 'tdm_ext' was expected >> >> >> > 'mclk_ext' was expected >> >> >> > 'pll0_out' was expected >> >> >> > From schema: /Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml >> >> >> > /tmp/tmp.KDlzwQM5ma/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.2a.dtb: clock-controller@13020000: clocks: 'oneOf' conditional failed, one must be fixed: >> >> >> > [[19], [20], [21], [22], [23], [24], [25], [26], [27]] is too short >> >> >> > From schema: Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml >> >> >> > /tmp/tmp.KDlzwQM5ma/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.2a.dtb: clock-controller@13020000: clock-names: 'oneOf' conditional failed, one must be fixed: >> >> >> > ['osc', 'gmac1_rmii_refin', 'gmac1_rgmii_rxin', 'i2stx_bclk_ext', 'i2stx_lrck_ext', 'i2srx_bclk_ext', 'i2srx_lrck_ext', 'tdm_ext', 'mclk_ext'] is too short >> >> >> > 'i2stx_bclk_ext' was expected >> >> >> > 'i2stx_lrck_ext' was expected >> >> >> > 'i2srx_bclk_ext' was expected >> >> >> > 'i2srx_lrck_ext' was expected >> >> >> > 'tdm_ext' was expected >> >> >> > 'mclk_ext' was expected >> >> >> > 'pll0_out' was expected >> >> >> > Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml >> >> >> > >> >> >> > This binding change is incompatible with the existing devicetrees for >> >> >> > the visionfive 2. >> >> >> >> >> >> This looks like less clocks about PLL in SYSCRG node. And I add this in patch 7. >> >> > >> >> > The existing devicetree is a valid, albeit limited, description of the >> >> > hardware. >> >> > After your changes to the clock driver in this series, but *without* the >> >> > changes to the devicetrees, does the system still function? >> >> > From a quick check of 4/7, it looks like it will not? >> >> >> >> I just tested it on the board and the system still worked without the changes >> >> about devicetree. But these clocks' rate were 0 because these could not get >> >> the PLL clocks from devicetree. >> > >> > Hmm, that sounds like an issue to me. If all of the clock rates are >> > computed based off of parents that incorrectly report 0, are we not in >> > for trouble? >> > Should the fixed-factor clocks be retained as a fallback for the sake of >> > compatibility? >> > Emil, Stephen? >> >> I got your concern. Actually, I can add a check in driver to see if the dts >> has pll clocks and then decide whether to use fixed-factor clocks or pll clocks >> from syscon. But eventually we have to use pll clocks and dts has to add it. >> Then the binding should add it synchronously, right? > > IMO, it is okay to change the bindings to only allow the "correct" > representation of the clock tree, but the driver should fall back to the > fixed factor clocks if it detects the old/limited configuration. > Great, I will follow it. Best regards, Xingyu Wu
diff --git a/Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml b/Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml index 84373ae31644..fcb363353050 100644 --- a/Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml +++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml @@ -27,6 +27,9 @@ properties: - description: External I2S RX left/right channel clock - description: External TDM clock - description: External audio master clock + - description: PLL0 + - description: PLL1 + - description: PLL2 - items: - description: Main Oscillator (24 MHz) @@ -38,6 +41,9 @@ properties: - description: External I2S RX left/right channel clock - description: External TDM clock - description: External audio master clock + - description: PLL0 + - description: PLL1 + - description: PLL2 clock-names: oneOf: @@ -52,6 +58,9 @@ properties: - const: i2srx_lrck_ext - const: tdm_ext - const: mclk_ext + - const: pll0_out + - const: pll1_out + - const: pll2_out - items: - const: osc @@ -63,6 +72,9 @@ properties: - const: i2srx_lrck_ext - const: tdm_ext - const: mclk_ext + - const: pll0_out + - const: pll1_out + - const: pll2_out '#clock-cells': const: 1 @@ -93,12 +105,16 @@ examples: <&gmac1_rgmii_rxin>, <&i2stx_bclk_ext>, <&i2stx_lrck_ext>, <&i2srx_bclk_ext>, <&i2srx_lrck_ext>, - <&tdm_ext>, <&mclk_ext>; + <&tdm_ext>, <&mclk_ext>, + <&pllclk 0>, + <&pllclk 1>, + <&pllclk 2>; clock-names = "osc", "gmac1_rmii_refin", "gmac1_rgmii_rxin", "i2stx_bclk_ext", "i2stx_lrck_ext", "i2srx_bclk_ext", "i2srx_lrck_ext", - "tdm_ext", "mclk_ext"; + "tdm_ext", "mclk_ext", + "pll0_out", "pll1_out", "pll2_out"; #clock-cells = <1>; #reset-cells = <1>; };