ARM: remove asm/locks.h

Commit Message

Paul Bolle July 2, 2012, 8:49 p.m. UTC

Commit 64ac24e738823161693bf791f87adc802cf529ff ("Generic semaphore
implementation") removed the last include of this header. Apparently it
was just an oversight to keep this header. It can safely be removed now.

Signed-off-by: Paul Bolle <[e-mail]>
---
Tested only with various git commands on the (history of the) tree.

 arch/arm/include/asm/locks.h |  274 ------------------------------------------
 1 files changed, 0 insertions(+), 274 deletions(-)
 delete mode 100644 arch/arm/include/asm/locks.h

Comments

Will Deacon July 2, 2012, 9:52 p.m. UTC | #1

Hi Paul,

On Mon, Jul 02, 2012 at 09:49:48PM +0100, Paul Bolle wrote:
> Commit 64ac24e738823161693bf791f87adc802cf529ff ("Generic semaphore
> implementation") removed the last include of this header. Apparently it
> was just an oversight to keep this header. It can safely be removed now.

Hmm, looks like you're right!

Acked-by: Will Deacon <[e-mail]>

> Tested only with various git commands on the (history of the) tree.

Not sure I follow, but since this is all dead code I can't see any tests
failing without it.

Will

Paul Bolle July 3, 2012, 7:20 a.m. UTC | #2

Will,

On Mon, 2012-07-02 at 22:52 +0100, Will Deacon wrote:
> On Mon, Jul 02, 2012 at 09:49:48PM +0100, Paul Bolle wrote:
> > Tested only with various git commands on the (history of the) tree.
> 
> Not sure I follow, but since this is all dead code I can't see any tests
> failing without it.

The purpose of that disclaimer is to stress that only git commands were
used to determine that removing this header is correct and safe. But
perhaps saying that I therefore "tested" this patch with git commands is
confusing.


Paul Bolle

Will Deacon July 8, 2012, 4:03 p.m. UTC | #3

On Tue, Jul 03, 2012 at 08:20:30AM +0100, Paul Bolle wrote:
> On Mon, 2012-07-02 at 22:52 +0100, Will Deacon wrote:
> > Not sure I follow, but since this is all dead code I can't see any tests
> > failing without it.
> 
> The purpose of that disclaimer is to stress that only git commands were
> used to determine that removing this header is correct and safe. But
> perhaps saying that I therefore "tested" this patch with git commands is
> confusing.

Okey doke. Please can you put this into the patch system?

Cheers,

Will

Paul Bolle July 8, 2012, 6:45 p.m. UTC | #4

On Sun, 2012-07-08 at 17:03 +0100, Will Deacon wrote:
>  Please can you put this into the patch system?

I'm not sure what the patch system is, but I am certain that I'm not
allowed to put this patch into it.


Paul Bolle

Will Deacon July 8, 2012, 9:57 p.m. UTC | #5

On Sun, Jul 08, 2012 at 07:45:06PM +0100, Paul Bolle wrote:
> On Sun, 2012-07-08 at 17:03 +0100, Will Deacon wrote:
> >  Please can you put this into the patch system?
> 
> I'm not sure what the patch system is, but I am certain that I'm not
> allowed to put this patch into it.

Don't be so certain -- the patch system is the preferred method for submitting
patches to arch/arm/ via Russell's tree. Since you're not familiar with it,
I've sent the patch for you this time:

  http://www.arm.linux.org.uk/developer/patches/viewpatch.php?id=7460/1

but if you have any additional patches to core ARM code then you can send
them following mailing list review and looking at the help here:

  http://www.arm.linux.org.uk/developer/patches/info.php

Note that changes to soc-specific code goes via the arm-soc tree (Arnd and
Olof) so don't use the patch system for that.

Cheers,

Will

Russell King - ARM Linux July 9, 2012, 8:32 a.m. UTC | #6

On Sun, Jul 08, 2012 at 10:57:12PM +0100, Will Deacon wrote:
> On Sun, Jul 08, 2012 at 07:45:06PM +0100, Paul Bolle wrote:
> > On Sun, 2012-07-08 at 17:03 +0100, Will Deacon wrote:
> > >  Please can you put this into the patch system?
> > 
> > I'm not sure what the patch system is, but I am certain that I'm not
> > allowed to put this patch into it.
> 
> Don't be so certain -- the patch system is the preferred method for submitting
> patches to arch/arm/ via Russell's tree. Since you're not familiar with it,
> I've sent the patch for you this time:
> 
>   http://www.arm.linux.org.uk/developer/patches/viewpatch.php?id=7460/1

Thanks Will.

And this will be a very good thing; I am going to be away for a little
over two weeks, and I'm not intending to read much email, neither am I
intending to catch up on the huge amount of email that will be unread
after the period.  This means that any patches buried in that email will
simply be ignored by me.

Patches in the patch system will get processed once I'm back though.

But, that doesn't mean "throw your patches into the patch system" - they
still need to be reviewed by someone (and any which appear in there
without an acked-by or reviewed-by or tested-by will be discarded unless
they're trivial.)

Patch

diff --git a/arch/arm/include/asm/locks.h b/arch/arm/include/asm/locks.h
deleted file mode 100644
index ef4c897..0000000
--- a/arch/arm/include/asm/locks.h
+++ /dev/null
@@ -1,274 +0,0 @@ 
-/*
- *  arch/arm/include/asm/locks.h
- *
- *  Copyright (C) 2000 Russell King
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- *  Interrupt safe locking assembler. 
- */
-#ifndef __ASM_PROC_LOCKS_H
-#define __ASM_PROC_LOCKS_H
-
-#if __LINUX_ARM_ARCH__ >= 6
-
-#define __down_op(ptr,fail)			\
-	({					\
-	__asm__ __volatile__(			\
-	"@ down_op\n"				\
-"1:	ldrex	lr, [%0]\n"			\
-"	sub	lr, lr, %1\n"			\
-"	strex	ip, lr, [%0]\n"			\
-"	teq	ip, #0\n"			\
-"	bne	1b\n"				\
-"	teq	lr, #0\n"			\
-"	movmi	ip, %0\n"			\
-"	blmi	" #fail				\
-	:					\
-	: "r" (ptr), "I" (1)			\
-	: "ip", "lr", "cc");			\
-	smp_mb();				\
-	})
-
-#define __down_op_ret(ptr,fail)			\
-	({					\
-		unsigned int ret;		\
-	__asm__ __volatile__(			\
-	"@ down_op_ret\n"			\
-"1:	ldrex	lr, [%1]\n"			\
-"	sub	lr, lr, %2\n"			\
-"	strex	ip, lr, [%1]\n"			\
-"	teq	ip, #0\n"			\
-"	bne	1b\n"				\
-"	teq	lr, #0\n"			\
-"	movmi	ip, %1\n"			\
-"	movpl	ip, #0\n"			\
-"	blmi	" #fail "\n"			\
-"	mov	%0, ip"				\
-	: "=&r" (ret)				\
-	: "r" (ptr), "I" (1)			\
-	: "ip", "lr", "cc");			\
-	smp_mb();				\
-	ret;					\
-	})
-
-#define __up_op(ptr,wake)			\
-	({					\
-	smp_mb();				\
-	__asm__ __volatile__(			\
-	"@ up_op\n"				\
-"1:	ldrex	lr, [%0]\n"			\
-"	add	lr, lr, %1\n"			\
-"	strex	ip, lr, [%0]\n"			\
-"	teq	ip, #0\n"			\
-"	bne	1b\n"				\
-"	cmp	lr, #0\n"			\
-"	movle	ip, %0\n"			\
-"	blle	" #wake				\
-	:					\
-	: "r" (ptr), "I" (1)			\
-	: "ip", "lr", "cc");			\
-	})
-
-/*
- * The value 0x01000000 supports up to 128 processors and
- * lots of processes.  BIAS must be chosen such that sub'ing
- * BIAS once per CPU will result in the long remaining
- * negative.
- */
-#define RW_LOCK_BIAS      0x01000000
-#define RW_LOCK_BIAS_STR "0x01000000"
-
-#define __down_op_write(ptr,fail)		\
-	({					\
-	__asm__ __volatile__(			\
-	"@ down_op_write\n"			\
-"1:	ldrex	lr, [%0]\n"			\
-"	sub	lr, lr, %1\n"			\
-"	strex	ip, lr, [%0]\n"			\
-"	teq	ip, #0\n"			\
-"	bne	1b\n"				\
-"	teq	lr, #0\n"			\
-"	movne	ip, %0\n"			\
-"	blne	" #fail				\
-	:					\
-	: "r" (ptr), "I" (RW_LOCK_BIAS)		\
-	: "ip", "lr", "cc");			\
-	smp_mb();				\
-	})
-
-#define __up_op_write(ptr,wake)			\
-	({					\
-	smp_mb();				\
-	__asm__ __volatile__(			\
-	"@ up_op_write\n"			\
-"1:	ldrex	lr, [%0]\n"			\
-"	adds	lr, lr, %1\n"			\
-"	strex	ip, lr, [%0]\n"			\
-"	teq	ip, #0\n"			\
-"	bne	1b\n"				\
-"	movcs	ip, %0\n"			\
-"	blcs	" #wake				\
-	:					\
-	: "r" (ptr), "I" (RW_LOCK_BIAS)		\
-	: "ip", "lr", "cc");			\
-	})
-
-#define __down_op_read(ptr,fail)		\
-	__down_op(ptr, fail)
-
-#define __up_op_read(ptr,wake)			\
-	({					\
-	smp_mb();				\
-	__asm__ __volatile__(			\
-	"@ up_op_read\n"			\
-"1:	ldrex	lr, [%0]\n"			\
-"	add	lr, lr, %1\n"			\
-"	strex	ip, lr, [%0]\n"			\
-"	teq	ip, #0\n"			\
-"	bne	1b\n"				\
-"	teq	lr, #0\n"			\
-"	moveq	ip, %0\n"			\
-"	bleq	" #wake				\
-	:					\
-	: "r" (ptr), "I" (1)			\
-	: "ip", "lr", "cc");			\
-	})
-
-#else
-
-#define __down_op(ptr,fail)			\
-	({					\
-	__asm__ __volatile__(			\
-	"@ down_op\n"				\
-"	mrs	ip, cpsr\n"			\
-"	orr	lr, ip, #128\n"			\
-"	msr	cpsr_c, lr\n"			\
-"	ldr	lr, [%0]\n"			\
-"	subs	lr, lr, %1\n"			\
-"	str	lr, [%0]\n"			\
-"	msr	cpsr_c, ip\n"			\
-"	movmi	ip, %0\n"			\
-"	blmi	" #fail				\
-	:					\
-	: "r" (ptr), "I" (1)			\
-	: "ip", "lr", "cc");			\
-	smp_mb();				\
-	})
-
-#define __down_op_ret(ptr,fail)			\
-	({					\
-		unsigned int ret;		\
-	__asm__ __volatile__(			\
-	"@ down_op_ret\n"			\
-"	mrs	ip, cpsr\n"			\
-"	orr	lr, ip, #128\n"			\
-"	msr	cpsr_c, lr\n"			\
-"	ldr	lr, [%1]\n"			\
-"	subs	lr, lr, %2\n"			\
-"	str	lr, [%1]\n"			\
-"	msr	cpsr_c, ip\n"			\
-"	movmi	ip, %1\n"			\
-"	movpl	ip, #0\n"			\
-"	blmi	" #fail "\n"			\
-"	mov	%0, ip"				\
-	: "=&r" (ret)				\
-	: "r" (ptr), "I" (1)			\
-	: "ip", "lr", "cc");			\
-	smp_mb();				\
-	ret;					\
-	})
-
-#define __up_op(ptr,wake)			\
-	({					\
-	smp_mb();				\
-	__asm__ __volatile__(			\
-	"@ up_op\n"				\
-"	mrs	ip, cpsr\n"			\
-"	orr	lr, ip, #128\n"			\
-"	msr	cpsr_c, lr\n"			\
-"	ldr	lr, [%0]\n"			\
-"	adds	lr, lr, %1\n"			\
-"	str	lr, [%0]\n"			\
-"	msr	cpsr_c, ip\n"			\
-"	movle	ip, %0\n"			\
-"	blle	" #wake				\
-	:					\
-	: "r" (ptr), "I" (1)			\
-	: "ip", "lr", "cc");			\
-	})
-
-/*
- * The value 0x01000000 supports up to 128 processors and
- * lots of processes.  BIAS must be chosen such that sub'ing
- * BIAS once per CPU will result in the long remaining
- * negative.
- */
-#define RW_LOCK_BIAS      0x01000000
-#define RW_LOCK_BIAS_STR "0x01000000"
-
-#define __down_op_write(ptr,fail)		\
-	({					\
-	__asm__ __volatile__(			\
-	"@ down_op_write\n"			\
-"	mrs	ip, cpsr\n"			\
-"	orr	lr, ip, #128\n"			\
-"	msr	cpsr_c, lr\n"			\
-"	ldr	lr, [%0]\n"			\
-"	subs	lr, lr, %1\n"			\
-"	str	lr, [%0]\n"			\
-"	msr	cpsr_c, ip\n"			\
-"	movne	ip, %0\n"			\
-"	blne	" #fail				\
-	:					\
-	: "r" (ptr), "I" (RW_LOCK_BIAS)		\
-	: "ip", "lr", "cc");			\
-	smp_mb();				\
-	})
-
-#define __up_op_write(ptr,wake)			\
-	({					\
-	__asm__ __volatile__(			\
-	"@ up_op_write\n"			\
-"	mrs	ip, cpsr\n"			\
-"	orr	lr, ip, #128\n"			\
-"	msr	cpsr_c, lr\n"			\
-"	ldr	lr, [%0]\n"			\
-"	adds	lr, lr, %1\n"			\
-"	str	lr, [%0]\n"			\
-"	msr	cpsr_c, ip\n"			\
-"	movcs	ip, %0\n"			\
-"	blcs	" #wake				\
-	:					\
-	: "r" (ptr), "I" (RW_LOCK_BIAS)		\
-	: "ip", "lr", "cc");			\
-	smp_mb();				\
-	})
-
-#define __down_op_read(ptr,fail)		\
-	__down_op(ptr, fail)
-
-#define __up_op_read(ptr,wake)			\
-	({					\
-	smp_mb();				\
-	__asm__ __volatile__(			\
-	"@ up_op_read\n"			\
-"	mrs	ip, cpsr\n"			\
-"	orr	lr, ip, #128\n"			\
-"	msr	cpsr_c, lr\n"			\
-"	ldr	lr, [%0]\n"			\
-"	adds	lr, lr, %1\n"			\
-"	str	lr, [%0]\n"			\
-"	msr	cpsr_c, ip\n"			\
-"	moveq	ip, %0\n"			\
-"	bleq	" #wake				\
-	:					\
-	: "r" (ptr), "I" (1)			\
-	: "ip", "lr", "cc");			\
-	})
-
-#endif
-
-#endif