| Message ID | 20230414062545.270178-4-chao.gao@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Intel IA32_SPEC_CTRL Virtualization | expand |
On 4/14/2023 2:25 PM, Chao Gao wrote: > From: Zhang Chen <chen.zhang@intel.com> > > Add 100% kvm-only feature for BHI_CTRL because the kernel doesn't use it > at all. > > BHI_CTRL is enumerated by CPUID.7.2.EDX[4]. If supported, BHI_DIS_S (bit > 10) of IA32_SPEC_CTRL MSR can be used to enable BHI_DIS_S behavior. > > Note that KVM does not intercept guests' IA32_SPEC_CTRL MSR accesses > after a non-zero is written to the MSR. Therefore, guests can already > toggle the BHI_DIS_S bit if the host supports BHI_CTRL, and no extra > code is needed to allow guests to toggle the bit. Same as Patch 2, please first fix virtualization of MSR_IA32_SPEC_CTRL. Otherwise the this patch makes no sense. E.g, if only X86_FEATURE_BHI_CTRL is exposed to guest without any other CPUID bits related to MSR_IA32_SPEC_CTRL, then guest cannot write MSR_IA32_SPEC_CTRL at all. > Signed-off-by: Zhang Chen <chen.zhang@intel.com> > Signed-off-by: Chao Gao <chao.gao@intel.com> > Tested-by: Jiaan Lu <jiaan.lu@intel.com> > --- > arch/x86/kvm/cpuid.c | 2 +- > arch/x86/kvm/reverse_cpuid.h | 1 + > 2 files changed, 2 insertions(+), 1 deletion(-) > > diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c > index f024c3ac2203..7cdd859d09a2 100644 > --- a/arch/x86/kvm/cpuid.c > +++ b/arch/x86/kvm/cpuid.c > @@ -686,7 +686,7 @@ void kvm_set_cpu_caps(void) > ); > > kvm_cpu_cap_init_kvm_defined(CPUID_7_2_EDX, > - SF(RRSBA_CTRL) > + SF(RRSBA_CTRL) | F(BHI_CTRL) > ); > > kvm_cpu_cap_mask(CPUID_8000_0001_ECX, > diff --git a/arch/x86/kvm/reverse_cpuid.h b/arch/x86/kvm/reverse_cpuid.h > index 72bad8314a9c..e7e70c9aa384 100644 > --- a/arch/x86/kvm/reverse_cpuid.h > +++ b/arch/x86/kvm/reverse_cpuid.h > @@ -50,6 +50,7 @@ enum kvm_only_cpuid_leafs { > > /* Intel-defined sub-features, CPUID level 0x00000007:2 (EDX) */ > #define KVM_X86_FEATURE_RRSBA_CTRL KVM_X86_FEATURE(CPUID_7_2_EDX, 2) > +#define X86_FEATURE_BHI_CTRL KVM_X86_FEATURE(CPUID_7_2_EDX, 4) > > struct cpuid_reg { > u32 function;
diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c index f024c3ac2203..7cdd859d09a2 100644 --- a/arch/x86/kvm/cpuid.c +++ b/arch/x86/kvm/cpuid.c @@ -686,7 +686,7 @@ void kvm_set_cpu_caps(void) ); kvm_cpu_cap_init_kvm_defined(CPUID_7_2_EDX, - SF(RRSBA_CTRL) + SF(RRSBA_CTRL) | F(BHI_CTRL) ); kvm_cpu_cap_mask(CPUID_8000_0001_ECX, diff --git a/arch/x86/kvm/reverse_cpuid.h b/arch/x86/kvm/reverse_cpuid.h index 72bad8314a9c..e7e70c9aa384 100644 --- a/arch/x86/kvm/reverse_cpuid.h +++ b/arch/x86/kvm/reverse_cpuid.h @@ -50,6 +50,7 @@ enum kvm_only_cpuid_leafs { /* Intel-defined sub-features, CPUID level 0x00000007:2 (EDX) */ #define KVM_X86_FEATURE_RRSBA_CTRL KVM_X86_FEATURE(CPUID_7_2_EDX, 2) +#define X86_FEATURE_BHI_CTRL KVM_X86_FEATURE(CPUID_7_2_EDX, 4) struct cpuid_reg { u32 function;