| Message ID | b4c9dcfbfc328e9404be0edeaa70dde076cb7144.1683630932.git.quic_varada@quicinc.com |
|---|---|
| State | Handled Elsewhere |
| Headers | show |
| Series | Enable IPQ9754 USB | expand |
On 5/9/2023 5:24 PM, Varadarajan Narayanan wrote: > Add USB phy and controller related nodes > > SS PHY need two supplies and HS PHY needs three supplies. 0.925V > and 3.3V are from fixed regulators and 1.8V is generated from > PMIC's LDO > > Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> > --- > Changes in v11: > - Rename dwc_0 -> usb_0_dwc3 > Changes in v10: > - Fix regulator definitions > Changes in v8: > - Change clocks order to match the bindings > Changes in v7: > - Change com_aux -> cfg_ahb > Changes in v6: > - Introduce fixed regulators for the phy > - Resolved all 'make dtbs_check' messages > > Changes in v5: > - Fix additional comments > - Edit nodes to match with qcom,sc8280xp-qmp-usb3-uni-phy.yaml > - 'make dtbs_check' giving the following messages since > ipq9574 doesn't have power domains. Hope this is ok > > /local/mnt/workspace/varada/varda-linux/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dtb: phy@7d000: 'power-domains' is a required property > From schema: /local/mnt/workspace/varada/varda-linux/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml > /local/mnt/workspace/varada/varda-linux/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dtb: usb@8a00000: 'power-domains' is a required property > From schema: /local/mnt/workspace/varada/varda-linux/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml > > Changes in v4: > - Use newer bindings without subnodes > - Fix coding style issues > > Changes in v3: > - Insert the nodes at proper location > > Changes in v2: > - Fixed issues flagged by Krzysztof > - Fix issues reported by make dtbs_check > - Remove NOC related clocks (to be added with proper > interconnect support) > --- > arch/arm64/boot/dts/qcom/ipq9574.dtsi | 104 ++++++++++++++++++++++++++++++++++ > 1 file changed, 104 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi > index 93b4ba9..42b61f6 100644 > --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi > +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi > @@ -150,6 +150,24 @@ > method = "smc"; > }; > > + fixed_3p3: s3300 { > + compatible = "regulator-fixed"; > + regulator-min-microvolt = <3300000>; > + regulator-max-microvolt = <3300000>; > + regulator-boot-on; > + regulator-always-on; > + regulator-name = "fixed_3p3"; > + }; > + > + fixed_0p925: s0925 { > + compatible = "regulator-fixed"; > + regulator-min-microvolt = <925000>; > + regulator-max-microvolt = <925000>; > + regulator-boot-on; > + regulator-always-on; > + regulator-name = "fixed_0p925"; > + }; > + > reserved-memory { > #address-cells = <2>; > #size-cells = <2>; > @@ -191,6 +209,45 @@ > reg = <0x00060000 0x6000>; > }; > > + usb_0_qusbphy: phy@7b000 { > + compatible = "qcom,ipq9574-qusb2-phy"; > + reg = <0x0007b000 0x180>; > + #phy-cells = <0>; > + > + clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, > + <&xo_board_clk>; > + clock-names = "cfg_ahb", > + "ref"; > + > + resets = <&gcc GCC_QUSB2_0_PHY_BCR>; > + status = "disabled"; > + }; > + > + usb_0_qmpphy: phy@7d000 { > + compatible = "qcom,ipq9574-qmp-usb3-phy"; > + reg = <0x0007d000 0xa00>; > + #phy-cells = <0>; > + > + clocks = <&gcc GCC_USB0_AUX_CLK>, > + <&xo_board_clk>, > + <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, > + <&gcc GCC_USB0_PIPE_CLK>; > + clock-names = "aux", > + "ref", > + "cfg_ahb", > + "pipe"; > + > + resets = <&gcc GCC_USB0_PHY_BCR>, > + <&gcc GCC_USB3PHY_0_PHY_BCR>; > + reset-names = "phy", > + "phy_phy"; > + > + status = "disabled"; > + > + #clock-cells = <0>; > + clock-output-names = "usb0_pipe_clk"; > + }; > + > pcie0_phy: phy@84000 { > compatible = "qcom,ipq9574-qmp-gen3x1-pcie-phy"; > reg = <0x00084000 0x1000>; > @@ -560,6 +617,53 @@ > status = "disabled"; > }; > > + usb3: usb@8a00000 { node address should be updated to 8af8800 ? Thanks,
On Mon, May 15, 2023 at 04:06:29PM +0530, Kathiravan T wrote: > > On 5/9/2023 5:24 PM, Varadarajan Narayanan wrote: > >Add USB phy and controller related nodes > > > >SS PHY need two supplies and HS PHY needs three supplies. 0.925V > >and 3.3V are from fixed regulators and 1.8V is generated from > >PMIC's LDO > > > >Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > >Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> > >--- > > Changes in v11: > > - Rename dwc_0 -> usb_0_dwc3 > > Changes in v10: > > - Fix regulator definitions > > Changes in v8: > > - Change clocks order to match the bindings > > Changes in v7: > > - Change com_aux -> cfg_ahb > > Changes in v6: > > - Introduce fixed regulators for the phy > > - Resolved all 'make dtbs_check' messages > > > > Changes in v5: > > - Fix additional comments > > - Edit nodes to match with qcom,sc8280xp-qmp-usb3-uni-phy.yaml > > - 'make dtbs_check' giving the following messages since > > ipq9574 doesn't have power domains. Hope this is ok > > > > /local/mnt/workspace/varada/varda-linux/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dtb: phy@7d000: 'power-domains' is a required property > > From schema: /local/mnt/workspace/varada/varda-linux/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml > > /local/mnt/workspace/varada/varda-linux/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dtb: usb@8a00000: 'power-domains' is a required property > > From schema: /local/mnt/workspace/varada/varda-linux/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml > > > > Changes in v4: > > - Use newer bindings without subnodes > > - Fix coding style issues > > > > Changes in v3: > > - Insert the nodes at proper location > > > > Changes in v2: > > - Fixed issues flagged by Krzysztof > > - Fix issues reported by make dtbs_check > > - Remove NOC related clocks (to be added with proper > > interconnect support) > >--- > > arch/arm64/boot/dts/qcom/ipq9574.dtsi | 104 ++++++++++++++++++++++++++++++++++ > > 1 file changed, 104 insertions(+) > > > >diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi > >index 93b4ba9..42b61f6 100644 > >--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi > >+++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi > >@@ -150,6 +150,24 @@ > > method = "smc"; > > }; > >+ fixed_3p3: s3300 { > >+ compatible = "regulator-fixed"; > >+ regulator-min-microvolt = <3300000>; > >+ regulator-max-microvolt = <3300000>; > >+ regulator-boot-on; > >+ regulator-always-on; > >+ regulator-name = "fixed_3p3"; > >+ }; > >+ > >+ fixed_0p925: s0925 { > >+ compatible = "regulator-fixed"; > >+ regulator-min-microvolt = <925000>; > >+ regulator-max-microvolt = <925000>; > >+ regulator-boot-on; > >+ regulator-always-on; > >+ regulator-name = "fixed_0p925"; > >+ }; > >+ > > reserved-memory { > > #address-cells = <2>; > > #size-cells = <2>; > >@@ -191,6 +209,45 @@ > > reg = <0x00060000 0x6000>; > > }; > >+ usb_0_qusbphy: phy@7b000 { > >+ compatible = "qcom,ipq9574-qusb2-phy"; > >+ reg = <0x0007b000 0x180>; > >+ #phy-cells = <0>; > >+ > >+ clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, > >+ <&xo_board_clk>; > >+ clock-names = "cfg_ahb", > >+ "ref"; > >+ > >+ resets = <&gcc GCC_QUSB2_0_PHY_BCR>; > >+ status = "disabled"; > >+ }; > >+ > >+ usb_0_qmpphy: phy@7d000 { > >+ compatible = "qcom,ipq9574-qmp-usb3-phy"; > >+ reg = <0x0007d000 0xa00>; > >+ #phy-cells = <0>; > >+ > >+ clocks = <&gcc GCC_USB0_AUX_CLK>, > >+ <&xo_board_clk>, > >+ <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, > >+ <&gcc GCC_USB0_PIPE_CLK>; > >+ clock-names = "aux", > >+ "ref", > >+ "cfg_ahb", > >+ "pipe"; > >+ > >+ resets = <&gcc GCC_USB0_PHY_BCR>, > >+ <&gcc GCC_USB3PHY_0_PHY_BCR>; > >+ reset-names = "phy", > >+ "phy_phy"; > >+ > >+ status = "disabled"; > >+ > >+ #clock-cells = <0>; > >+ clock-output-names = "usb0_pipe_clk"; > >+ }; > >+ > > pcie0_phy: phy@84000 { > > compatible = "qcom,ipq9574-qmp-gen3x1-pcie-phy"; > > reg = <0x00084000 0x1000>; > >@@ -560,6 +617,53 @@ > > status = "disabled"; > > }; > >+ usb3: usb@8a00000 { > > node address should be updated to 8af8800 ? Ok. Will update and post a new patchset. Thanks Varada
diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi index 93b4ba9..42b61f6 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -150,6 +150,24 @@ method = "smc"; }; + fixed_3p3: s3300 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + regulator-name = "fixed_3p3"; + }; + + fixed_0p925: s0925 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <925000>; + regulator-max-microvolt = <925000>; + regulator-boot-on; + regulator-always-on; + regulator-name = "fixed_0p925"; + }; + reserved-memory { #address-cells = <2>; #size-cells = <2>; @@ -191,6 +209,45 @@ reg = <0x00060000 0x6000>; }; + usb_0_qusbphy: phy@7b000 { + compatible = "qcom,ipq9574-qusb2-phy"; + reg = <0x0007b000 0x180>; + #phy-cells = <0>; + + clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, + <&xo_board_clk>; + clock-names = "cfg_ahb", + "ref"; + + resets = <&gcc GCC_QUSB2_0_PHY_BCR>; + status = "disabled"; + }; + + usb_0_qmpphy: phy@7d000 { + compatible = "qcom,ipq9574-qmp-usb3-phy"; + reg = <0x0007d000 0xa00>; + #phy-cells = <0>; + + clocks = <&gcc GCC_USB0_AUX_CLK>, + <&xo_board_clk>, + <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, + <&gcc GCC_USB0_PIPE_CLK>; + clock-names = "aux", + "ref", + "cfg_ahb", + "pipe"; + + resets = <&gcc GCC_USB0_PHY_BCR>, + <&gcc GCC_USB3PHY_0_PHY_BCR>; + reset-names = "phy", + "phy_phy"; + + status = "disabled"; + + #clock-cells = <0>; + clock-output-names = "usb0_pipe_clk"; + }; + pcie0_phy: phy@84000 { compatible = "qcom,ipq9574-qmp-gen3x1-pcie-phy"; reg = <0x00084000 0x1000>; @@ -560,6 +617,53 @@ status = "disabled"; }; + usb3: usb@8a00000 { + compatible = "qcom,ipq9574-dwc3", "qcom,dwc3"; + reg = <0x08af8800 0x400>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + clocks = <&gcc GCC_SNOC_USB_CLK>, + <&gcc GCC_USB0_MASTER_CLK>, + <&gcc GCC_ANOC_USB_AXI_CLK>, + <&gcc GCC_USB0_SLEEP_CLK>, + <&gcc GCC_USB0_MOCK_UTMI_CLK>; + + clock-names = "cfg_noc", + "core", + "iface", + "sleep", + "mock_utmi"; + + assigned-clocks = <&gcc GCC_USB0_MASTER_CLK>, + <&gcc GCC_USB0_MOCK_UTMI_CLK>; + assigned-clock-rates = <200000000>, + <24000000>; + + interrupts-extended = <&intc GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pwr_event"; + + resets = <&gcc GCC_USB_BCR>; + status = "disabled"; + + usb_0_dwc3: usb@8a00000 { + compatible = "snps,dwc3"; + reg = <0x8a00000 0xcd00>; + clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>; + clock-names = "ref"; + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; + phys = <&usb_0_qusbphy>, <&usb_0_qmpphy>; + phy-names = "usb2-phy", "usb3-phy"; + tx-fifo-resize; + snps,is-utmi-l1-suspend; + snps,hird-threshold = /bits/ 8 <0x0>; + snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; + dr_mode = "host"; + }; + }; + intc: interrupt-controller@b000000 { compatible = "qcom,msm-qgic2"; reg = <0x0b000000 0x1000>, /* GICD */