| Message ID | 20230509161218.11979-5-quic_jkona@quicinc.com (mailing list archive) |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
| Series | Add Video Clock Controller driver for SM8550 | expand |
On 9.05.2023 18:12, Jagadeesh Kona wrote: > Add device node for video clock controller on Qualcomm SM8550 platform. > > Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> > Signed-off-by: Taniya Das <quic_tdas@quicinc.com> > --- > arch/arm64/boot/dts/qcom/sm8550.dtsi | 12 ++++++++++++ > 1 file changed, 12 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi > index 6e9bad8f6f33..e67e7c69dae6 100644 > --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi > @@ -7,6 +7,7 @@ > #include <dt-bindings/clock/qcom,sm8550-gcc.h> > #include <dt-bindings/clock/qcom,sm8550-tcsr.h> > #include <dt-bindings/clock/qcom,sm8550-dispcc.h> > +#include <dt-bindings/clock/qcom,sm8550-videocc.h> > #include <dt-bindings/dma/qcom-gpi.h> > #include <dt-bindings/gpio/gpio.h> > #include <dt-bindings/interrupt-controller/arm-gic.h> > @@ -759,6 +760,17 @@ gcc: clock-controller@100000 { > <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; > }; > > + videocc: clock-controller@aaf0000 { This node should be moved down. Nodes with unit addresses should be sorted alphanumerically. > + compatible = "qcom,sm8550-videocc"; > + reg = <0 0x0aaf0000 0 0x10000>; > + clocks = <&bi_tcxo_div2>, <&gcc GCC_VIDEO_AHB_CLK>; One per line, please Also, any reason the XO clock does not come from RPMhCC? Konrad > + power-domains = <&rpmhpd SM8550_MMCX>; > + required-opps = <&rpmhpd_opp_low_svs>; > + #clock-cells = <1>; > + #reset-cells = <1>; > + #power-domain-cells = <1>; > + }; > + > ipcc: mailbox@408000 { > compatible = "qcom,sm8550-ipcc", "qcom,ipcc"; > reg = <0 0x00408000 0 0x1000>;
On Mon, 15 May 2023 at 15:28, Konrad Dybcio <konrad.dybcio@linaro.org> wrote: > > > > On 9.05.2023 18:12, Jagadeesh Kona wrote: > > Add device node for video clock controller on Qualcomm SM8550 platform. > > > > Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> > > Signed-off-by: Taniya Das <quic_tdas@quicinc.com> > > --- > > arch/arm64/boot/dts/qcom/sm8550.dtsi | 12 ++++++++++++ > > 1 file changed, 12 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi > > index 6e9bad8f6f33..e67e7c69dae6 100644 > > --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi > > +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi > > @@ -7,6 +7,7 @@ > > #include <dt-bindings/clock/qcom,sm8550-gcc.h> > > #include <dt-bindings/clock/qcom,sm8550-tcsr.h> > > #include <dt-bindings/clock/qcom,sm8550-dispcc.h> > > +#include <dt-bindings/clock/qcom,sm8550-videocc.h> > > #include <dt-bindings/dma/qcom-gpi.h> > > #include <dt-bindings/gpio/gpio.h> > > #include <dt-bindings/interrupt-controller/arm-gic.h> > > @@ -759,6 +760,17 @@ gcc: clock-controller@100000 { > > <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; > > }; > > > > + videocc: clock-controller@aaf0000 { > This node should be moved down. Nodes with unit addresses > should be sorted alphanumerically. > > > + compatible = "qcom,sm8550-videocc"; > > + reg = <0 0x0aaf0000 0 0x10000>; > > + clocks = <&bi_tcxo_div2>, <&gcc GCC_VIDEO_AHB_CLK>; > One per line, please > > Also, any reason the XO clock does not come from RPMhCC? bi_tcxo_div_2 is an RPMhCC clock with the fixed divider. > > Konrad > > + power-domains = <&rpmhpd SM8550_MMCX>; > > + required-opps = <&rpmhpd_opp_low_svs>; > > + #clock-cells = <1>; > > + #reset-cells = <1>; > > + #power-domain-cells = <1>; > > + }; > > + > > ipcc: mailbox@408000 { > > compatible = "qcom,sm8550-ipcc", "qcom,ipcc"; > > reg = <0 0x00408000 0 0x1000>;
On 15.05.2023 14:57, Dmitry Baryshkov wrote: > On Mon, 15 May 2023 at 15:28, Konrad Dybcio <konrad.dybcio@linaro.org> wrote: >> >> >> >> On 9.05.2023 18:12, Jagadeesh Kona wrote: >>> Add device node for video clock controller on Qualcomm SM8550 platform. >>> >>> Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> >>> Signed-off-by: Taniya Das <quic_tdas@quicinc.com> >>> --- >>> arch/arm64/boot/dts/qcom/sm8550.dtsi | 12 ++++++++++++ >>> 1 file changed, 12 insertions(+) >>> >>> diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi >>> index 6e9bad8f6f33..e67e7c69dae6 100644 >>> --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi >>> +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi >>> @@ -7,6 +7,7 @@ >>> #include <dt-bindings/clock/qcom,sm8550-gcc.h> >>> #include <dt-bindings/clock/qcom,sm8550-tcsr.h> >>> #include <dt-bindings/clock/qcom,sm8550-dispcc.h> >>> +#include <dt-bindings/clock/qcom,sm8550-videocc.h> >>> #include <dt-bindings/dma/qcom-gpi.h> >>> #include <dt-bindings/gpio/gpio.h> >>> #include <dt-bindings/interrupt-controller/arm-gic.h> >>> @@ -759,6 +760,17 @@ gcc: clock-controller@100000 { >>> <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; >>> }; >>> >>> + videocc: clock-controller@aaf0000 { >> This node should be moved down. Nodes with unit addresses >> should be sorted alphanumerically. >> >>> + compatible = "qcom,sm8550-videocc"; >>> + reg = <0 0x0aaf0000 0 0x10000>; >>> + clocks = <&bi_tcxo_div2>, <&gcc GCC_VIDEO_AHB_CLK>; >> One per line, please >> >> Also, any reason the XO clock does not come from RPMhCC? > > bi_tcxo_div_2 is an RPMhCC clock with the fixed divider. Hm, I don't see it neither on -next or in this patchset.. Konrad > >> >> Konrad >>> + power-domains = <&rpmhpd SM8550_MMCX>; >>> + required-opps = <&rpmhpd_opp_low_svs>; >>> + #clock-cells = <1>; >>> + #reset-cells = <1>; >>> + #power-domain-cells = <1>; >>> + }; >>> + >>> ipcc: mailbox@408000 { >>> compatible = "qcom,sm8550-ipcc", "qcom,ipcc"; >>> reg = <0 0x00408000 0 0x1000>; > > >
On Mon, 15 May 2023 at 16:08, Konrad Dybcio <konrad.dybcio@linaro.org> wrote: > > > > On 15.05.2023 14:57, Dmitry Baryshkov wrote: > > On Mon, 15 May 2023 at 15:28, Konrad Dybcio <konrad.dybcio@linaro.org> wrote: > >> > >> > >> > >> On 9.05.2023 18:12, Jagadeesh Kona wrote: > >>> Add device node for video clock controller on Qualcomm SM8550 platform. > >>> > >>> Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> > >>> Signed-off-by: Taniya Das <quic_tdas@quicinc.com> > >>> --- > >>> arch/arm64/boot/dts/qcom/sm8550.dtsi | 12 ++++++++++++ > >>> 1 file changed, 12 insertions(+) > >>> > >>> diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi > >>> index 6e9bad8f6f33..e67e7c69dae6 100644 > >>> --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi > >>> +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi > >>> @@ -7,6 +7,7 @@ > >>> #include <dt-bindings/clock/qcom,sm8550-gcc.h> > >>> #include <dt-bindings/clock/qcom,sm8550-tcsr.h> > >>> #include <dt-bindings/clock/qcom,sm8550-dispcc.h> > >>> +#include <dt-bindings/clock/qcom,sm8550-videocc.h> > >>> #include <dt-bindings/dma/qcom-gpi.h> > >>> #include <dt-bindings/gpio/gpio.h> > >>> #include <dt-bindings/interrupt-controller/arm-gic.h> > >>> @@ -759,6 +760,17 @@ gcc: clock-controller@100000 { > >>> <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; > >>> }; > >>> > >>> + videocc: clock-controller@aaf0000 { > >> This node should be moved down. Nodes with unit addresses > >> should be sorted alphanumerically. > >> > >>> + compatible = "qcom,sm8550-videocc"; > >>> + reg = <0 0x0aaf0000 0 0x10000>; > >>> + clocks = <&bi_tcxo_div2>, <&gcc GCC_VIDEO_AHB_CLK>; > >> One per line, please > >> > >> Also, any reason the XO clock does not come from RPMhCC? > > > > bi_tcxo_div_2 is an RPMhCC clock with the fixed divider. > Hm, I don't see it neither on -next or in this patchset.. https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/arch/arm64/boot/dts/qcom/sm8550.dtsi?h=next-20230515#n41
Hi, Thanks Konrad for your review! On 5/15/2023 5:58 PM, Konrad Dybcio wrote: > > > On 9.05.2023 18:12, Jagadeesh Kona wrote: >> Add device node for video clock controller on Qualcomm SM8550 platform. >> >> Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> >> Signed-off-by: Taniya Das <quic_tdas@quicinc.com> >> --- >> arch/arm64/boot/dts/qcom/sm8550.dtsi | 12 ++++++++++++ >> 1 file changed, 12 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi >> index 6e9bad8f6f33..e67e7c69dae6 100644 >> --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi >> @@ -7,6 +7,7 @@ >> #include <dt-bindings/clock/qcom,sm8550-gcc.h> >> #include <dt-bindings/clock/qcom,sm8550-tcsr.h> >> #include <dt-bindings/clock/qcom,sm8550-dispcc.h> >> +#include <dt-bindings/clock/qcom,sm8550-videocc.h> >> #include <dt-bindings/dma/qcom-gpi.h> >> #include <dt-bindings/gpio/gpio.h> >> #include <dt-bindings/interrupt-controller/arm-gic.h> >> @@ -759,6 +760,17 @@ gcc: clock-controller@100000 { >> <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; >> }; >> >> + videocc: clock-controller@aaf0000 { > This node should be moved down. Nodes with unit addresses > should be sorted alphanumerically. > Sure, will update in the next series. >> + compatible = "qcom,sm8550-videocc"; >> + reg = <0 0x0aaf0000 0 0x10000>; >> + clocks = <&bi_tcxo_div2>, <&gcc GCC_VIDEO_AHB_CLK>; > One per line, please > Okay > Also, any reason the XO clock does not come from RPMhCC? > > Konrad >> + power-domains = <&rpmhpd SM8550_MMCX>; >> + required-opps = <&rpmhpd_opp_low_svs>; >> + #clock-cells = <1>; >> + #reset-cells = <1>; >> + #power-domain-cells = <1>; >> + }; >> + >> ipcc: mailbox@408000 { >> compatible = "qcom,sm8550-ipcc", "qcom,ipcc"; >> reg = <0 0x00408000 0 0x1000>; Thanks & Regards, Jagadeesh
diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 6e9bad8f6f33..e67e7c69dae6 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -7,6 +7,7 @@ #include <dt-bindings/clock/qcom,sm8550-gcc.h> #include <dt-bindings/clock/qcom,sm8550-tcsr.h> #include <dt-bindings/clock/qcom,sm8550-dispcc.h> +#include <dt-bindings/clock/qcom,sm8550-videocc.h> #include <dt-bindings/dma/qcom-gpi.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/arm-gic.h> @@ -759,6 +760,17 @@ gcc: clock-controller@100000 { <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; }; + videocc: clock-controller@aaf0000 { + compatible = "qcom,sm8550-videocc"; + reg = <0 0x0aaf0000 0 0x10000>; + clocks = <&bi_tcxo_div2>, <&gcc GCC_VIDEO_AHB_CLK>; + power-domains = <&rpmhpd SM8550_MMCX>; + required-opps = <&rpmhpd_opp_low_svs>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + ipcc: mailbox@408000 { compatible = "qcom,sm8550-ipcc", "qcom,ipcc"; reg = <0 0x00408000 0 0x1000>;