diff mbox series

arm64: dts: ti: k3-j7200: correct num-lanes requested for PCIe

Message ID 20230516062212.2635948-1-a-verma1@ti.com (mailing list archive)
State New, archived
Headers show
Series arm64: dts: ti: k3-j7200: correct num-lanes requested for PCIe | expand

Commit Message

Achal Verma May 16, 2023, 6:22 a.m. UTC 
From: Matt Ranostay <mranostay@ti.com>

J7200 has a limited 2x support for PCIe, and the properties should be
updated as such.

Signed-off-by: Matt Ranostay <mranostay@ti.com>
Signed-off-by: Achal Verma <a-verma1@ti.com>
---
 arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

Comments

Siddharth Vadapalli May 16, 2023, 6:33 a.m. UTC | #1 
Achal,

On 16/05/23 11:52, Achal Verma wrote:
> From: Matt Ranostay <mranostay@ti.com>
> 
> J7200 has a limited 2x support for PCIe, and the properties should be
> updated as such.

According to J7200 Datasheet at [0], the SoC supports up to x4 PCIe lanes. Could
you please clarify where the lanes are documented to be 2x?

[0]: https://www.ti.com/lit/ds/symlink/dra821u-q1.pdf

> 
> Signed-off-by: Matt Ranostay <mranostay@ti.com>
> Signed-off-by: Achal Verma <a-verma1@ti.com>
> ---
>  arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
> index ef352e32f19d..5e62b431d6e8 100644
> --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
> @@ -729,7 +729,7 @@ pcie1_rc: pcie@2910000 {
>  		device_type = "pci";
>  		ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
>  		max-link-speed = <3>;
> -		num-lanes = <4>;
> +		num-lanes = <2>;
>  		power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
>  		clocks = <&k3_clks 240 6>;
>  		clock-names = "fck";
> @@ -757,7 +757,7 @@ pcie1_ep: pcie-ep@2910000 {
>  		interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
>  		ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
>  		max-link-speed = <3>;
> -		num-lanes = <4>;
> +		num-lanes = <2>;
>  		power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
>  		clocks = <&k3_clks 240 6>;
>  		clock-names = "fck";
Achal Verma May 16, 2023, 9:01 a.m. UTC | #2 
On 5/16/2023 12:03 PM, Siddharth Vadapalli wrote:
> Achal,
> 
> On 16/05/23 11:52, Achal Verma wrote:
>> From: Matt Ranostay <mranostay@ti.com>
>>
>> J7200 has a limited 2x support for PCIe, and the properties should be
>> updated as such.
> 
> According to J7200 Datasheet at [0], the SoC supports up to x4 PCIe lanes. Could
> you please clarify where the lanes are documented to be 2x?
> 
> [0]: https://www.ti.com/lit/ds/symlink/dra821u-q1.pdf

Yes, this patch should be dropped.
No need to change lanes.

Regards,
Achal Verma
> 
>>
>> Signed-off-by: Matt Ranostay <mranostay@ti.com>
>> Signed-off-by: Achal Verma <a-verma1@ti.com>
>> ---
>>   arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 4 ++--
>>   1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
>> index ef352e32f19d..5e62b431d6e8 100644
>> --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
>> +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
>> @@ -729,7 +729,7 @@ pcie1_rc: pcie@2910000 {
>>   		device_type = "pci";
>>   		ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
>>   		max-link-speed = <3>;
>> -		num-lanes = <4>;
>> +		num-lanes = <2>;
>>   		power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
>>   		clocks = <&k3_clks 240 6>;
>>   		clock-names = "fck";
>> @@ -757,7 +757,7 @@ pcie1_ep: pcie-ep@2910000 {
>>   		interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
>>   		ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
>>   		max-link-speed = <3>;
>> -		num-lanes = <4>;
>> +		num-lanes = <2>;
>>   		power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
>>   		clocks = <&k3_clks 240 6>;
>>   		clock-names = "fck";
>
Nishanth Menon May 16, 2023, 1:13 p.m. UTC | #3 
On 11:52-20230516, Achal Verma wrote:
> From: Matt Ranostay <mranostay@ti.com>
> 
> J7200 has a limited 2x support for PCIe, and the properties should be
> updated as such.
> 

What commit does this fix?

> Signed-off-by: Matt Ranostay <mranostay@ti.com>
> Signed-off-by: Achal Verma <a-verma1@ti.com>
> ---
>  arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
> index ef352e32f19d..5e62b431d6e8 100644
> --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
> @@ -729,7 +729,7 @@ pcie1_rc: pcie@2910000 {
>  		device_type = "pci";
>  		ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
>  		max-link-speed = <3>;
> -		num-lanes = <4>;
> +		num-lanes = <2>;
>  		power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
>  		clocks = <&k3_clks 240 6>;
>  		clock-names = "fck";
> @@ -757,7 +757,7 @@ pcie1_ep: pcie-ep@2910000 {
>  		interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
>  		ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
>  		max-link-speed = <3>;
> -		num-lanes = <4>;
> +		num-lanes = <2>;
>  		power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
>  		clocks = <&k3_clks 240 6>;
>  		clock-names = "fck";
> -- 
> 2.25.1
>
Achal Verma May 16, 2023, 4:24 p.m. UTC | #4 
On 5/16/2023 6:43 PM, Nishanth Menon wrote:
> On 11:52-20230516, Achal Verma wrote:
>> From: Matt Ranostay <mranostay@ti.com>
>>
>> J7200 has a limited 2x support for PCIe, and the properties should be
>> updated as such.
>>
> 
> What commit does this fix?
This patch is a mistake.
J7200 PCIe has 4 lanes, and this patch should be dropped.

Regards,
Achal Verma
> 
>> Signed-off-by: Matt Ranostay <mranostay@ti.com>
>> Signed-off-by: Achal Verma <a-verma1@ti.com>
>> ---
>>   arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 4 ++--
>>   1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
>> index ef352e32f19d..5e62b431d6e8 100644
>> --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
>> +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
>> @@ -729,7 +729,7 @@ pcie1_rc: pcie@2910000 {
>>   		device_type = "pci";
>>   		ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
>>   		max-link-speed = <3>;
>> -		num-lanes = <4>;
>> +		num-lanes = <2>;
>>   		power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
>>   		clocks = <&k3_clks 240 6>;
>>   		clock-names = "fck";
>> @@ -757,7 +757,7 @@ pcie1_ep: pcie-ep@2910000 {
>>   		interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
>>   		ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
>>   		max-link-speed = <3>;
>> -		num-lanes = <4>;
>> +		num-lanes = <2>;
>>   		power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
>>   		clocks = <&k3_clks 240 6>;
>>   		clock-names = "fck";
>> -- 
>> 2.25.1
>>
> 
>
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
index ef352e32f19d..5e62b431d6e8 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
@@ -729,7 +729,7 @@  pcie1_rc: pcie@2910000 {
 		device_type = "pci";
 		ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
 		max-link-speed = <3>;
-		num-lanes = <4>;
+		num-lanes = <2>;
 		power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
 		clocks = <&k3_clks 240 6>;
 		clock-names = "fck";
@@ -757,7 +757,7 @@  pcie1_ep: pcie-ep@2910000 {
 		interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
 		ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
 		max-link-speed = <3>;
-		num-lanes = <4>;
+		num-lanes = <2>;
 		power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
 		clocks = <&k3_clks 240 6>;
 		clock-names = "fck";