[-next,v20,23/26] riscv: Enable Vector code to be built

Message ID	20230518161949.11203-24-andy.chiu@sifive.com (mailing list archive)
State	New, archived
Headers	show Return-Path: <kvm-owner@vger.kernel.org> From: Andy Chiu <andy.chiu@sifive.com> To: linux-riscv@lists.infradead.org, palmer@dabbelt.com, anup@brainfault.org, atishp@atishpatra.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: vineetg@rivosinc.com, greentime.hu@sifive.com, guoren@linux.alibaba.com, Andy Chiu <andy.chiu@sifive.com>, Paul Walmsley <paul.walmsley@sifive.com>, Albert Ou <aou@eecs.berkeley.edu> Subject: [PATCH -next v20 23/26] riscv: Enable Vector code to be built Date: Thu, 18 May 2023 16:19:46 +0000 Message-Id: <20230518161949.11203-24-andy.chiu@sifive.com> In-Reply-To: <20230518161949.11203-1-andy.chiu@sifive.com> References: <20230518161949.11203-1-andy.chiu@sifive.com> Precedence: bulk
Series	riscv: Add vector ISA support \| expand [-next,v20,00/26] riscv: Add vector ISA support [-next,v20,01/26] riscv: Rename __switch_to_aux() -> fpu [-next,v20,02/26] riscv: Extending cpufeature.c to detect V-extension [-next,v20,03/26] riscv: hwprobe: Add support for probing V in RISCV_HWPROBE_KEY_IMA_EXT_0 [-next,v20,04/26] riscv: Add new csr defines related to vector extension [-next,v20,05/26] riscv: Clear vector regfile on bootup [-next,v20,06/26] riscv: Disable Vector Instructions for kernel itself [-next,v20,07/26] riscv: Introduce Vector enable/disable helpers [-next,v20,08/26] riscv: Introduce riscv_v_vsize to record size of Vector context [-next,v20,09/26] riscv: Introduce struct/helpers to save/restore per-task Vector state [-next,v20,10/26] riscv: Add task switch support for vector [-next,v20,11/26] riscv: Allocate user's vector context in the first-use trap [-next,v20,12/26] riscv: Add ptrace vector support [-next,v20,13/26] riscv: signal: check fp-reserved words unconditionally [-next,v20,14/26] riscv: signal: Add sigcontext save/restore for vector [-next,v20,15/26] riscv: signal: Report signal frame size to userspace via auxv [-next,v20,16/26] riscv: signal: validate altstack to reflect Vector [-next,v20,17/26] riscv: prevent stack corruption by reserving task_pt_regs(p) early [-next,v20,18/26] riscv: kvm: Add V extension to KVM ISA [-next,v20,19/26] riscv: KVM: Add vector lazy save/restore support [-next,v20,20/26] riscv: Add prctl controls for userspace vector management [-next,v20,21/26] riscv: Add sysctl to set the default vector rule for new processes [-next,v20,22/26] riscv: detect assembler support for .option arch [-next,v20,23/26] riscv: Enable Vector code to be built [-next,v20,24/26] riscv: Add documentation for Vector [-next,v20,25/26] selftests: Test RISC-V Vector prctl interface [-next,v20,26/26] selftests: add .gitignore file for RISC-V hwprobe

Message ID

20230518161949.11203-24-andy.chiu@sifive.com (mailing list archive)

State

New, archived

Headers

From: Andy Chiu <andy.chiu@sifive.com>
To: linux-riscv@lists.infradead.org, palmer@dabbelt.com,
        anup@brainfault.org, atishp@atishpatra.org,
        kvm-riscv@lists.infradead.org, kvm@vger.kernel.org
Cc: vineetg@rivosinc.com, greentime.hu@sifive.com,
        guoren@linux.alibaba.com, Andy Chiu <andy.chiu@sifive.com>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        Albert Ou <aou@eecs.berkeley.edu>
Subject: [PATCH -next v20 23/26] riscv: Enable Vector code to be built
Date: Thu, 18 May 2023 16:19:46 +0000
Message-Id: <20230518161949.11203-24-andy.chiu@sifive.com>
In-Reply-To: <20230518161949.11203-1-andy.chiu@sifive.com>
References: <20230518161949.11203-1-andy.chiu@sifive.com>
Precedence: bulk

Series

riscv: Add vector ISA support | expand

Commit Message

Andy Chiu May 18, 2023, 4:19 p.m. UTC

From: Guo Ren <guoren@linux.alibaba.com>

This patch adds configs for building Vector code. First it detects the
reqired toolchain support for building the code. Then it provides an
option setting whether Vector is implicitly enabled to userspace.

Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
Co-developed-by: Greentime Hu <greentime.hu@sifive.com>
Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
Suggested-by: Conor Dooley <conor.dooley@microchip.com>>
Co-developed-by: Andy Chiu <andy.chiu@sifive.com>
Signed-off-by: Andy Chiu <andy.chiu@sifive.com>
---
Changelog v20:
 - s/RISCV_V_DISABLE/RISCV_ISA_V_DEFAULT_ENABLE/ for better
   understanding (Conor)
 - Update commit message (Conor)
Changelog V19:
 - Add RISCV_V_DISABLE to set compile-time default.
---
 arch/riscv/Kconfig  | 31 +++++++++++++++++++++++++++++++
 arch/riscv/Makefile |  6 +++++-
 2 files changed, 36 insertions(+), 1 deletion(-)

Comments

Conor Dooley May 18, 2023, 5:31 p.m. UTC | #1

On Thu, May 18, 2023 at 04:19:46PM +0000, Andy Chiu wrote:
> From: Guo Ren <guoren@linux.alibaba.com>
> 
> This patch adds configs for building Vector code. First it detects the
> reqired toolchain support for building the code. Then it provides an
> option setting whether Vector is implicitly enabled to userspace.
> 
> Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
> Co-developed-by: Greentime Hu <greentime.hu@sifive.com>
> Signed-off-by: Greentime Hu <greentime.hu@sifive.com>

> Suggested-by: Conor Dooley <conor.dooley@microchip.com>>

You can drop this tag if you respin, I just provided review comments ;)
Also, it has an extra > at the end.

Otherwise, I am still not sold on the "default y", but we can always
flip it if there is in fact a regression.

Reviewed-by: Conor Dooley <conor.dooley@microchip.com>

Thanks.

Palmer Dabbelt May 24, 2023, 12:22 a.m. UTC | #2

On Thu, 18 May 2023 10:31:37 PDT (-0700), Conor Dooley wrote:
> On Thu, May 18, 2023 at 04:19:46PM +0000, Andy Chiu wrote:
>> From: Guo Ren <guoren@linux.alibaba.com>
>> 
>> This patch adds configs for building Vector code. First it detects the
>> reqired toolchain support for building the code. Then it provides an
>> option setting whether Vector is implicitly enabled to userspace.
>> 
>> Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
>> Co-developed-by: Greentime Hu <greentime.hu@sifive.com>
>> Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
>
>> Suggested-by: Conor Dooley <conor.dooley@microchip.com>>
>
> You can drop this tag if you respin, I just provided review comments ;)
> Also, it has an extra > at the end.
>
> Otherwise, I am still not sold on the "default y", but we can always
> flip it if there is in fact a regression.

It's definately the riskier of the options, but the uABI issue will only 
manifest on systems that have V hardware.  Those don't exist yet, so 
aside from folks running QEMU (who probably want V) we're only risking 
tripping up users on pre-release silicion -- and that's always a 
headache, so whatever ;)

> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
>
> Thanks.

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 1019b519d590..f3ba0a8b085e 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -466,6 +466,37 @@  config RISCV_ISA_SVPBMT
 
 	   If you don't know what to do here, say Y.
 
+config TOOLCHAIN_HAS_V
+	bool
+	default y
+	depends on !64BIT || $(cc-option,-mabi=lp64 -march=rv64iv)
+	depends on !32BIT || $(cc-option,-mabi=ilp32 -march=rv32iv)
+	depends on LLD_VERSION >= 140000 || LD_VERSION >= 23800
+	depends on AS_HAS_OPTION_ARCH
+
+config RISCV_ISA_V
+	bool "VECTOR extension support"
+	depends on TOOLCHAIN_HAS_V
+	depends on FPU
+	select DYNAMIC_SIGFRAME
+	default y
+	help
+	  Say N here if you want to disable all vector related procedure
+	  in the kernel.
+
+	  If you don't know what to do here, say Y.
+
+config RISCV_ISA_V_DEFAULT_ENABLE
+	bool "Enable userspace Vector by default"
+	depends on RISCV_ISA_V
+	default y
+	help
+	  Say Y here if you want to enable Vector in userspace by default.
+	  Otherwise, userspace has to make explicit prctl() call to enable
+	  Vector, or enable it via the sysctl interface.
+
+	  If you don't know what to do here, say Y.
+
 config TOOLCHAIN_HAS_ZBB
 	bool
 	default y
diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
index 0fb256bf8270..6ec6d52a4180 100644
--- a/arch/riscv/Makefile
+++ b/arch/riscv/Makefile
@@ -60,6 +60,7 @@  riscv-march-$(CONFIG_ARCH_RV32I)	:= rv32ima
 riscv-march-$(CONFIG_ARCH_RV64I)	:= rv64ima
 riscv-march-$(CONFIG_FPU)		:= $(riscv-march-y)fd
 riscv-march-$(CONFIG_RISCV_ISA_C)	:= $(riscv-march-y)c
+riscv-march-$(CONFIG_RISCV_ISA_V)	:= $(riscv-march-y)v
 
 ifdef CONFIG_TOOLCHAIN_NEEDS_OLD_ISA_SPEC
 KBUILD_CFLAGS += -Wa,-misa-spec=2.2
@@ -71,7 +72,10 @@  endif
 # Check if the toolchain supports Zihintpause extension
 riscv-march-$(CONFIG_TOOLCHAIN_HAS_ZIHINTPAUSE) := $(riscv-march-y)_zihintpause
 
-KBUILD_CFLAGS += -march=$(subst fd,,$(riscv-march-y))
+# Remove F,D,V from isa string for all. Keep extensions between "fd" and "v" by
+# matching non-v and non-multi-letter extensions out with the filter ([^v_]*)
+KBUILD_CFLAGS += -march=$(shell echo $(riscv-march-y) | sed -E 's/(rv32ima|rv64ima)fd([^v_]*)v?/\1\2/')
+
 KBUILD_AFLAGS += -march=$(riscv-march-y)
 
 KBUILD_CFLAGS += -mno-save-restore

[-next,v20,23/26] riscv: Enable Vector code to be built

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