Message ID | 20230518161949.11203-22-andy.chiu@sifive.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | riscv: Add vector ISA support | expand |
Andy Chiu <andy.chiu@sifive.com> writes: > To support Vector extension, the series exports variable-length vector > registers on the signal frame. However, this potentially breaks abi if > processing vector registers is required in the signal handler for old > binaries. For example, there is such need if user-level context switch > is triggerred via signals[1]. > > For this reason, it is best to leave a decision to distro maintainers, > where the enablement of userspace Vector for new launching programs can > be controlled. Developers may also need the switch to experiment with. > The parameter is configurable through sysctl interface so a distro may > turn off Vector early at init script if the break really happens in the > wild. > > The switch will only take effects on new execve() calls once set. This > will not effect existing processes that do not call execve(), nor > processes which has been set with a non-default vstate_ctrl by making > explicit PR_RISCV_V_SET_CONTROL prctl() calls. > > Link: https://lore.kernel.org/all/87cz4048rp.fsf@all.your.base.are.belong.to.us/ > Signed-off-by: Andy Chiu <andy.chiu@sifive.com> > Reviewed-by: Greentime Hu <greentime.hu@sifive.com> > Reviewed-by: Vincent Chen <vincent.chen@sifive.com> > --- > Changelog v20: > - Use READ_ONCE to access riscv_v_implicit_uacc (Björn) Reviewed-by: Björn Töpel <bjorn@rivosinc.com>
diff --git a/arch/riscv/kernel/vector.c b/arch/riscv/kernel/vector.c index 9bee7a201106..25c7f5c93b00 100644 --- a/arch/riscv/kernel/vector.c +++ b/arch/riscv/kernel/vector.c @@ -184,7 +184,7 @@ void riscv_v_vstate_ctrl_init(struct task_struct *tsk) next = riscv_v_ctrl_get_next(tsk); if (!next) { - if (riscv_v_implicit_uacc) + if (READ_ONCE(riscv_v_implicit_uacc)) cur = PR_RISCV_V_VSTATE_CTRL_ON; else cur = PR_RISCV_V_VSTATE_CTRL_OFF; @@ -247,3 +247,34 @@ long riscv_v_vstate_ctrl_set_current(unsigned long arg) return -EINVAL; } + +#ifdef CONFIG_SYSCTL + +static struct ctl_table riscv_v_default_vstate_table[] = { + { + .procname = "riscv_v_default_allow", + .data = &riscv_v_implicit_uacc, + .maxlen = sizeof(riscv_v_implicit_uacc), + .mode = 0644, + .proc_handler = proc_dobool, + }, + { } +}; + +static int __init riscv_v_sysctl_init(void) +{ + if (has_vector()) + if (!register_sysctl("abi", riscv_v_default_vstate_table)) + return -EINVAL; + return 0; +} + +#else /* ! CONFIG_SYSCTL */ +static int __init riscv_v_sysctl_init(void) { return 0; } +#endif /* ! CONFIG_SYSCTL */ + +static int riscv_v_init(void) +{ + return riscv_v_sysctl_init(); +} +core_initcall(riscv_v_init);