| Message ID | 20230518112750.57924-8-minda.chen@starfivetech.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Add JH7110 USB and USB PHY driver support | expand |
Greg, On Thu, May 18, 2023 at 07:27:50PM +0800, Minda Chen wrote: > Add USB wrapper layer and Cadence USB3 controller dts > configuration for StarFive JH7110 SoC and VisionFive2 > Board. > USB controller connect to PHY, The PHY dts configuration > are also added. > > Signed-off-by: Minda Chen <minda.chen@starfivetech.com> > diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi > index 71a8e9acbe55..b65f06c5b1b7 100644 > --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi > +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi > @@ -366,6 +366,59 @@ > status = "disabled"; > }; > > + usb0: usb@10100000 { > + compatible = "starfive,jh7110-usb"; > + ranges = <0x0 0x0 0x10100000 0x100000>; > + #address-cells = <1>; > + #size-cells = <1>; > + starfive,stg-syscon = <&stg_syscon 0x4>; > + clocks = <&stgcrg JH7110_STGCLK_USB0_LPM>, Please don't pick this patch, if the rest of the series is applicable, as this will break building the dtb as stgcrg does not yet exist in any maintainer tree. Thanks, Conor.
On Thu, May 25, 2023 at 10:36:38PM +0100, Conor Dooley wrote: > Greg, > > On Thu, May 18, 2023 at 07:27:50PM +0800, Minda Chen wrote: > > Add USB wrapper layer and Cadence USB3 controller dts > > configuration for StarFive JH7110 SoC and VisionFive2 > > Board. > > USB controller connect to PHY, The PHY dts configuration > > are also added. > > > > Signed-off-by: Minda Chen <minda.chen@starfivetech.com> > > > diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi > > index 71a8e9acbe55..b65f06c5b1b7 100644 > > --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi > > +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi > > @@ -366,6 +366,59 @@ > > status = "disabled"; > > }; > > > > + usb0: usb@10100000 { > > + compatible = "starfive,jh7110-usb"; > > + ranges = <0x0 0x0 0x10100000 0x100000>; > > + #address-cells = <1>; > > + #size-cells = <1>; > > + starfive,stg-syscon = <&stg_syscon 0x4>; > > + clocks = <&stgcrg JH7110_STGCLK_USB0_LPM>, > > Please don't pick this patch, if the rest of the series is applicable, > as this will break building the dtb as stgcrg does not yet exist in any > maintainer tree. Ok, I'll just take patch 6/7 then. thanks, greg k-h
On Mon, May 29, 2023 at 03:46:21PM +0100, Greg Kroah-Hartman wrote: > On Thu, May 25, 2023 at 10:36:38PM +0100, Conor Dooley wrote: > > Greg, > > > > On Thu, May 18, 2023 at 07:27:50PM +0800, Minda Chen wrote: > > > Add USB wrapper layer and Cadence USB3 controller dts > > > configuration for StarFive JH7110 SoC and VisionFive2 > > > Board. > > > USB controller connect to PHY, The PHY dts configuration > > > are also added. > > > > > > Signed-off-by: Minda Chen <minda.chen@starfivetech.com> > > > > > diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi > > > index 71a8e9acbe55..b65f06c5b1b7 100644 > > > --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi > > > +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi > > > @@ -366,6 +366,59 @@ > > > status = "disabled"; > > > }; > > > > > > + usb0: usb@10100000 { > > > + compatible = "starfive,jh7110-usb"; > > > + ranges = <0x0 0x0 0x10100000 0x100000>; > > > + #address-cells = <1>; > > > + #size-cells = <1>; > > > + starfive,stg-syscon = <&stg_syscon 0x4>; > > > + clocks = <&stgcrg JH7110_STGCLK_USB0_LPM>, > > > > Please don't pick this patch, if the rest of the series is applicable, > > as this will break building the dtb as stgcrg does not yet exist in any > > maintainer tree. > > Ok, I'll just take patch 6/7 then. I think I missed this mail somehow. 5/7 had the binding for the driver so probably that should've gone via the USB tree too? Should apply on its own (no deps on the phy patches) & has dt-binding maintainer reviews. `b4 am -P 5 20230518112750.57924-6-minda.chen@starfivetech.com` if that's your cup of tea. Cheers, Conor.
diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi index 1155b97b593d..934453bc80d5 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi @@ -221,3 +221,8 @@ pinctrl-0 = <&uart0_pins>; status = "okay"; }; + +&usb0 { + dr_mode = "peripheral"; + status = "okay"; +}; diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi index 71a8e9acbe55..b65f06c5b1b7 100644 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -366,6 +366,59 @@ status = "disabled"; }; + usb0: usb@10100000 { + compatible = "starfive,jh7110-usb"; + ranges = <0x0 0x0 0x10100000 0x100000>; + #address-cells = <1>; + #size-cells = <1>; + starfive,stg-syscon = <&stg_syscon 0x4>; + clocks = <&stgcrg JH7110_STGCLK_USB0_LPM>, + <&stgcrg JH7110_STGCLK_USB0_STB>, + <&stgcrg JH7110_STGCLK_USB0_APB>, + <&stgcrg JH7110_STGCLK_USB0_AXI>, + <&stgcrg JH7110_STGCLK_USB0_UTMI_APB>; + clock-names = "lpm", "stb", "apb", "axi", "utmi_apb"; + resets = <&stgcrg JH7110_STGRST_USB0_PWRUP>, + <&stgcrg JH7110_STGRST_USB0_APB>, + <&stgcrg JH7110_STGRST_USB0_AXI>, + <&stgcrg JH7110_STGRST_USB0_UTMI_APB>; + reset-names = "pwrup", "apb", "axi", "utmi_apb"; + status = "disabled"; + + usb_cdns3: usb@0 { + compatible = "cdns,usb3"; + reg = <0x0 0x10000>, + <0x10000 0x10000>, + <0x20000 0x10000>; + reg-names = "otg", "xhci", "dev"; + interrupts = <100>, <108>, <110>; + interrupt-names = "host", "peripheral", "otg"; + phys = <&usbphy0>; + phy-names = "cdns3,usb2-phy"; + }; + }; + + usbphy0: phy@10200000 { + compatible = "starfive,jh7110-usb-phy"; + reg = <0x0 0x10200000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_USB_125M>, + <&stgcrg JH7110_STGCLK_USB0_APP_125>; + clock-names = "125m", "app_125m"; + #phy-cells = <0>; + }; + + pciephy0: phy@10210000 { + compatible = "starfive,jh7110-pcie-phy"; + reg = <0x0 0x10210000 0x0 0x10000>; + #phy-cells = <0>; + }; + + pciephy1: phy@10220000 { + compatible = "starfive,jh7110-pcie-phy"; + reg = <0x0 0x10220000 0x0 0x10000>; + #phy-cells = <0>; + }; + stgcrg: clock-controller@10230000 { compatible = "starfive,jh7110-stgcrg"; reg = <0x0 0x10230000 0x0 0x10000>;
Add USB wrapper layer and Cadence USB3 controller dts configuration for StarFive JH7110 SoC and VisionFive2 Board. USB controller connect to PHY, The PHY dts configuration are also added. Signed-off-by: Minda Chen <minda.chen@starfivetech.com> --- .../jh7110-starfive-visionfive-2.dtsi | 5 ++ arch/riscv/boot/dts/starfive/jh7110.dtsi | 53 +++++++++++++++++++ 2 files changed, 58 insertions(+)