| Message ID | 20230602231754.1596433-2-matthew.s.atwood@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Update various *MAX_GT* definitions | expand |
On Fri, Jun 02, 2023 at 04:17:53PM -0700, Matt Atwood wrote: > According to Ashutosh there is no current or planned product in i915 for > I915_MAX_GT to be 4 anymore. > > Cc: Matt Roper <matthew.d.roper@intel.com> > Cc: Ashutosh Dixit <ashutosh.dixit@linux.intel.com> > Cc: Andi Shyti <andy.shyti@linux.intel.com> > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> > Cc: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com> > > Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com> MTL is the only platform where we've enabled multiple GTs at the moment (one primary, one media). Although multi-tile platforms could potentially have more, we haven't enabled multi-tile on i915 for xehpsdv and pvc, and will probably refocus that work on the Xe driver now. So reducing to 2 sounds fine. Reviewed-by: Matt Roper <matthew.d.roper@intel.com> > --- > drivers/gpu/drm/i915/i915_drv.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index f1205ed3ba71..c3923f52ca56 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -314,7 +314,7 @@ struct drm_i915_private { > /* > * i915->gt[0] == &i915->gt0 > */ > -#define I915_MAX_GT 4 > +#define I915_MAX_GT 2 > struct intel_gt *gt[I915_MAX_GT]; > > struct kobject *sysfs_gt; > -- > 2.40.0 >
On Fri, 02 Jun 2023 17:13:48 -0700, Matt Roper wrote: > > On Fri, Jun 02, 2023 at 04:17:53PM -0700, Matt Atwood wrote: > > According to Ashutosh there is no current or planned product in i915 for > > I915_MAX_GT to be 4 anymore. > > > > Cc: Matt Roper <matthew.d.roper@intel.com> > > Cc: Ashutosh Dixit <ashutosh.dixit@linux.intel.com> > > Cc: Andi Shyti <andy.shyti@linux.intel.com> > > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> > > Cc: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com> > > > > Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com> > > MTL is the only platform where we've enabled multiple GTs at the moment > (one primary, one media). Although multi-tile platforms could > potentially have more, we haven't enabled multi-tile on i915 for xehpsdv > and pvc, and will probably refocus that work on the Xe driver now. So > reducing to 2 sounds fine. > > Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Thanks Matt R for confirming reducing to 2 is ok: Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index f1205ed3ba71..c3923f52ca56 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -314,7 +314,7 @@ struct drm_i915_private { /* * i915->gt[0] == &i915->gt0 */ -#define I915_MAX_GT 4 +#define I915_MAX_GT 2 struct intel_gt *gt[I915_MAX_GT]; struct kobject *sysfs_gt;
According to Ashutosh there is no current or planned product in i915 for I915_MAX_GT to be 4 anymore. Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Ashutosh Dixit <ashutosh.dixit@linux.intel.com> Cc: Andi Shyti <andy.shyti@linux.intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com> Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)