| Message ID | 20230525122930.17141-3-srinivas.kandagatla@linaro.org (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | clk: qcom: sc8280xp: add lpasscc reset control | expand |
On Thu, May 25, 2023 at 01:29:26PM +0100, Srinivas Kandagatla wrote: > The LPASS (Low Power Audio Subsystem) Audio clock controller provides reset > support when it is under the control of Q6DSP. > > Add support for those resets and adds IDs for clients to request the reset. > > Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> > --- > .../bindings/clock/qcom,sc8280xp-lpasscc.yaml | 11 +++++++++++ > include/dt-bindings/clock/qcom,lpasscc-sc8280xp.h | 5 +++++ > 2 files changed, 16 insertions(+) > > diff --git a/Documentation/devicetree/bindings/clock/qcom,sc8280xp-lpasscc.yaml b/Documentation/devicetree/bindings/clock/qcom,sc8280xp-lpasscc.yaml > index 08a9ae60a365..0557e74d3c3b 100644 > --- a/Documentation/devicetree/bindings/clock/qcom,sc8280xp-lpasscc.yaml > +++ b/Documentation/devicetree/bindings/clock/qcom,sc8280xp-lpasscc.yaml > @@ -21,6 +21,7 @@ properties: > > compatible: > enum: > + - qcom,sc8280xp-lpassaudiocc > - qcom,sc8280xp-lpasscc > > qcom,adsp-pil-mode: > @@ -45,6 +46,16 @@ required: > additionalProperties: false > > examples: > + - | > + #include <dt-bindings/clock/qcom,lpasscc-sc8280xp.h> > + lpass_audiocc: clock-controller@32a9000 { > + compatible = "qcom,sc8280xp-lpassaudiocc"; > + reg = <0x032a9000 0x1000>; > + qcom,adsp-pil-mode; > + #reset-cells = <1>; > + #clock-cells = <1>; Nit: #clock before #reset > + }; > + > - | > #include <dt-bindings/clock/qcom,lpasscc-sc8280xp.h> > lpasscc: clock-controller@33e0000 { > diff --git a/include/dt-bindings/clock/qcom,lpasscc-sc8280xp.h b/include/dt-bindings/clock/qcom,lpasscc-sc8280xp.h > index df800ea2741c..d190d57fc81a 100644 > --- a/include/dt-bindings/clock/qcom,lpasscc-sc8280xp.h > +++ b/include/dt-bindings/clock/qcom,lpasscc-sc8280xp.h > @@ -6,6 +6,11 @@ > #ifndef _DT_BINDINGS_CLK_QCOM_LPASSCC_SC8280XP_H > #define _DT_BINDINGS_CLK_QCOM_LPASSCC_SC8280XP_H > > +/* LPASS AUDIO CC CSR */ > +#define LPASS_AUDIO_SWR_RX_CGCR 0 > +#define LPASS_AUDIO_SWR_WSA_CGCR 1 > +#define LPASS_AUDIO_SWR_WSA2_CGCR 2 > + > /* LPASS TCSR */ > #define LPASS_AUDIO_SWR_TX_CGCR 0 Should you have different prefixes for the CSR and TCSR defines? Looks good to me otherwise: Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
On 31/05/2023 20:59, Krzysztof Kozlowski wrote: > On 25/05/2023 14:29, Srinivas Kandagatla wrote: >> The LPASS (Low Power Audio Subsystem) Audio clock controller provides reset >> support when it is under the control of Q6DSP. >> > > A nit, subject: drop second/last, redundant "YAML schemas for". The > "dt-bindings" prefix is already stating that these are > bindings/schemas/YAML/etc. > > Same comment for first patch. > Thanks, will fix in v3 --srini > >> Add support for those resets and adds IDs for clients to request the reset. >> >> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> >> --- >> .../bindings/clock/qcom,sc8280xp-lpasscc.yaml | 11 +++++++++++ >> include/dt-bindings/clock/qcom,lpasscc-sc8280xp.h | 5 +++++ >> 2 files changed, 16 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/clock/qcom,sc8280xp-lpasscc.yaml b/Documentation/devicetree/bindings/clock/qcom,sc8280xp-lpasscc.yaml >> index 08a9ae60a365..0557e74d3c3b 100644 >> --- a/Documentation/devicetree/bindings/clock/qcom,sc8280xp-lpasscc.yaml >> +++ b/Documentation/devicetree/bindings/clock/qcom,sc8280xp-lpasscc.yaml >> @@ -21,6 +21,7 @@ properties: >> >> compatible: >> enum: >> + - qcom,sc8280xp-lpassaudiocc >> - qcom,sc8280xp-lpasscc >> >> qcom,adsp-pil-mode: >> @@ -45,6 +46,16 @@ required: >> additionalProperties: false >> >> examples: >> + - | >> + #include <dt-bindings/clock/qcom,lpasscc-sc8280xp.h> >> + lpass_audiocc: clock-controller@32a9000 { >> + compatible = "qcom,sc8280xp-lpassaudiocc"; >> + reg = <0x032a9000 0x1000>; >> + qcom,adsp-pil-mode; >> + #reset-cells = <1>; >> + #clock-cells = <1>; >> + }; > > No need for new example - it's basically the same. > > Best regards, > Krzysztof >
diff --git a/Documentation/devicetree/bindings/clock/qcom,sc8280xp-lpasscc.yaml b/Documentation/devicetree/bindings/clock/qcom,sc8280xp-lpasscc.yaml index 08a9ae60a365..0557e74d3c3b 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sc8280xp-lpasscc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sc8280xp-lpasscc.yaml @@ -21,6 +21,7 @@ properties: compatible: enum: + - qcom,sc8280xp-lpassaudiocc - qcom,sc8280xp-lpasscc qcom,adsp-pil-mode: @@ -45,6 +46,16 @@ required: additionalProperties: false examples: + - | + #include <dt-bindings/clock/qcom,lpasscc-sc8280xp.h> + lpass_audiocc: clock-controller@32a9000 { + compatible = "qcom,sc8280xp-lpassaudiocc"; + reg = <0x032a9000 0x1000>; + qcom,adsp-pil-mode; + #reset-cells = <1>; + #clock-cells = <1>; + }; + - | #include <dt-bindings/clock/qcom,lpasscc-sc8280xp.h> lpasscc: clock-controller@33e0000 { diff --git a/include/dt-bindings/clock/qcom,lpasscc-sc8280xp.h b/include/dt-bindings/clock/qcom,lpasscc-sc8280xp.h index df800ea2741c..d190d57fc81a 100644 --- a/include/dt-bindings/clock/qcom,lpasscc-sc8280xp.h +++ b/include/dt-bindings/clock/qcom,lpasscc-sc8280xp.h @@ -6,6 +6,11 @@ #ifndef _DT_BINDINGS_CLK_QCOM_LPASSCC_SC8280XP_H #define _DT_BINDINGS_CLK_QCOM_LPASSCC_SC8280XP_H +/* LPASS AUDIO CC CSR */ +#define LPASS_AUDIO_SWR_RX_CGCR 0 +#define LPASS_AUDIO_SWR_WSA_CGCR 1 +#define LPASS_AUDIO_SWR_WSA2_CGCR 2 + /* LPASS TCSR */ #define LPASS_AUDIO_SWR_TX_CGCR 0
The LPASS (Low Power Audio Subsystem) Audio clock controller provides reset support when it is under the control of Q6DSP. Add support for those resets and adds IDs for clients to request the reset. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> --- .../bindings/clock/qcom,sc8280xp-lpasscc.yaml | 11 +++++++++++ include/dt-bindings/clock/qcom,lpasscc-sc8280xp.h | 5 +++++ 2 files changed, 16 insertions(+)