| Message ID | 20230607221651.2454764-4-terry.bowman@amd.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | cxl/pci: Add support for RCH RAS error handling | expand |
Terry Bowman wrote: > From: Robert Richter <rrichter@amd.com> > > Reading code like dport->dport does not immediately suggest that this > points to the corresponding device structure of the dport. Rename > struct member @dport to @dev. This one I don't agree with. This can switch to ->dport_dev if you like. The reason for ->dport was for symmetry with the ->uport of a 'struct cxl_port'. So if you change this to ->dport_dev then also make the ->uport_dev change for symmetry. Unlike a 'struct cxl_port' a 'struct cxl_dport' is not a device in its own right which is what I see when I read dport->dev. > > While at it, also rename @new argument of add_dport() to @dport. This > better describes the variable as a dport (e.g. new->dport becomes to > dport->dev). There is already other occurrences of dport_dev as an argument, so I think that works here too.
Hi Dan, On 6/8/23 01:42, Dan Williams wrote: > Terry Bowman wrote: >> From: Robert Richter <rrichter@amd.com> >> >> Reading code like dport->dport does not immediately suggest that this >> points to the corresponding device structure of the dport. Rename >> struct member @dport to @dev. > > This one I don't agree with. > > This can switch to ->dport_dev if you like. The reason for ->dport was > for symmetry with the ->uport of a 'struct cxl_port'. So if you change > this to ->dport_dev then also make the ->uport_dev change for symmetry. > > Unlike a 'struct cxl_port' a 'struct cxl_dport' is not a device in its > own right which is what I see when I read dport->dev. > Ok, I'll change the structure member names and code to use the following: struct cxl_dport::dev -> struct cxl_dport::dport_dev struct cxl_port::uport -> struct cxl_port::uport_dev Regards, Terry >> >> While at it, also rename @new argument of add_dport() to @dport. This >> better describes the variable as a dport (e.g. new->dport becomes to >> dport->dev). > > There is already other occurrences of dport_dev as an argument, so I > think that works here too.
Terry Bowman wrote: > Hi Dan, > > > On 6/8/23 01:42, Dan Williams wrote: > > Terry Bowman wrote: > >> From: Robert Richter <rrichter@amd.com> > >> > >> Reading code like dport->dport does not immediately suggest that this > >> points to the corresponding device structure of the dport. Rename > >> struct member @dport to @dev. > > > > This one I don't agree with. > > > > This can switch to ->dport_dev if you like. The reason for ->dport was > > for symmetry with the ->uport of a 'struct cxl_port'. So if you change > > this to ->dport_dev then also make the ->uport_dev change for symmetry. > > > > Unlike a 'struct cxl_port' a 'struct cxl_dport' is not a device in its > > own right which is what I see when I read dport->dev. > > > > Ok, I'll change the structure member names and code to use the following: > struct cxl_dport::dev -> struct cxl_dport::dport_dev > > struct cxl_port::uport -> struct cxl_port::uport_dev Sounds good, to save duplication of work I already have this that you can just adopt: -- >8 -- Subject: cxl: Rename 'uport' to 'uport_dev' From: Dan Williams <dan.j.williams@intel.com> For symmetry with the recent rename of ->dport_dev for a 'struct cxl_dport', add the "_dev" suffix to the ->uport property of a 'struct cxl_port'. These devices represent the downstream-port-device and upstream-port-device respectively in the CXL/PCIe topology. Signed-off-by: Dan Williams <dan.j.williams@intel.com> --- drivers/cxl/core/pci.c | 4 +-- drivers/cxl/core/port.c | 61 ++++++++++++++++++++++------------------- drivers/cxl/core/region.c | 48 +++++++++++++++++--------------- drivers/cxl/cxl.h | 13 +++++---- drivers/cxl/cxlmem.h | 4 +-- drivers/cxl/mem.c | 2 + drivers/cxl/port.c | 2 + tools/testing/cxl/test/cxl.c | 20 +++++++------ tools/testing/cxl/test/mock.c | 10 +++---- 9 files changed, 86 insertions(+), 78 deletions(-) diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index 67f4ab6daa34..375f01c6cad6 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -67,7 +67,7 @@ static int match_add_dports(struct pci_dev *pdev, void *data) /** * devm_cxl_port_enumerate_dports - enumerate downstream ports of the upstream port - * @port: cxl_port whose ->uport is the upstream of dports to be enumerated + * @port: cxl_port whose ->uport_dev is the upstream of dports to be enumerated * * Returns a positive number of dports enumerated or a negative error * code. @@ -622,7 +622,7 @@ static int cxl_cdat_read_table(struct device *dev, */ void read_cdat_data(struct cxl_port *port) { - struct cxl_memdev *cxlmd = to_cxl_memdev(port->uport); + struct cxl_memdev *cxlmd = to_cxl_memdev(port->uport_dev); struct device *host = cxlmd->dev.parent; struct device *dev = &port->dev; struct pci_doe_mb *cdat_doe; diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c index 93800e6e095f..a45a063d52ce 100644 --- a/drivers/cxl/core/port.c +++ b/drivers/cxl/core/port.c @@ -561,9 +561,9 @@ static void unregister_port(void *_port) * unregistered while holding their parent port lock. */ if (!parent) - lock_dev = port->uport; + lock_dev = port->uport_dev; else if (is_cxl_root(parent)) - lock_dev = parent->uport; + lock_dev = parent->uport_dev; else lock_dev = &parent->dev; @@ -583,7 +583,8 @@ static int devm_cxl_link_uport(struct device *host, struct cxl_port *port) { int rc; - rc = sysfs_create_link(&port->dev.kobj, &port->uport->kobj, "uport"); + rc = sysfs_create_link(&port->dev.kobj, &port->uport_dev->kobj, + "uport"); if (rc) return rc; return devm_add_action_or_reset(host, cxl_unlink_uport, port); @@ -614,7 +615,7 @@ static int devm_cxl_link_parent_dport(struct device *host, static struct lock_class_key cxl_port_key; -static struct cxl_port *cxl_port_alloc(struct device *uport, +static struct cxl_port *cxl_port_alloc(struct device *uport_dev, resource_size_t component_reg_phys, struct cxl_dport *parent_dport) { @@ -630,7 +631,7 @@ static struct cxl_port *cxl_port_alloc(struct device *uport, if (rc < 0) goto err; port->id = rc; - port->uport = uport; + port->uport_dev = uport_dev; /* * The top-level cxl_port "cxl_root" does not have a cxl_port as @@ -660,10 +661,11 @@ static struct cxl_port *cxl_port_alloc(struct device *uport, else if (parent_dport->rch) port->host_bridge = parent_dport->dport_dev; else - port->host_bridge = iter->uport; - dev_dbg(uport, "host-bridge: %s\n", dev_name(port->host_bridge)); + port->host_bridge = iter->uport_dev; + dev_dbg(uport_dev, "host-bridge: %s\n", + dev_name(port->host_bridge)); } else - dev->parent = uport; + dev->parent = uport_dev; port->component_reg_phys = component_reg_phys; ida_init(&port->decoder_ida); @@ -687,7 +689,7 @@ static struct cxl_port *cxl_port_alloc(struct device *uport, } static struct cxl_port *__devm_cxl_add_port(struct device *host, - struct device *uport, + struct device *uport_dev, resource_size_t component_reg_phys, struct cxl_dport *parent_dport) { @@ -695,12 +697,12 @@ static struct cxl_port *__devm_cxl_add_port(struct device *host, struct device *dev; int rc; - port = cxl_port_alloc(uport, component_reg_phys, parent_dport); + port = cxl_port_alloc(uport_dev, component_reg_phys, parent_dport); if (IS_ERR(port)) return port; dev = &port->dev; - if (is_cxl_memdev(uport)) + if (is_cxl_memdev(uport_dev)) rc = dev_set_name(dev, "endpoint%d", port->id); else if (parent_dport) rc = dev_set_name(dev, "port%d", port->id); @@ -735,28 +737,29 @@ static struct cxl_port *__devm_cxl_add_port(struct device *host, /** * devm_cxl_add_port - register a cxl_port in CXL memory decode hierarchy * @host: host device for devm operations - * @uport: "physical" device implementing this upstream port + * @uport_dev: "physical" device implementing this upstream port * @component_reg_phys: (optional) for configurable cxl_port instances * @parent_dport: next hop up in the CXL memory decode hierarchy */ -struct cxl_port *devm_cxl_add_port(struct device *host, struct device *uport, +struct cxl_port *devm_cxl_add_port(struct device *host, + struct device *uport_dev, resource_size_t component_reg_phys, struct cxl_dport *parent_dport) { struct cxl_port *port, *parent_port; - port = __devm_cxl_add_port(host, uport, component_reg_phys, + port = __devm_cxl_add_port(host, uport_dev, component_reg_phys, parent_dport); parent_port = parent_dport ? parent_dport->port : NULL; if (IS_ERR(port)) { - dev_dbg(uport, "Failed to add%s%s%s: %ld\n", + dev_dbg(uport_dev, "Failed to add%s%s%s: %ld\n", parent_port ? " port to " : "", parent_port ? dev_name(&parent_port->dev) : "", parent_port ? "" : " root port", PTR_ERR(port)); } else { - dev_dbg(uport, "%s added%s%s%s\n", + dev_dbg(uport_dev, "%s added%s%s%s\n", dev_name(&port->dev), parent_port ? " to " : "", parent_port ? dev_name(&parent_port->dev) : "", @@ -773,33 +776,34 @@ struct pci_bus *cxl_port_to_pci_bus(struct cxl_port *port) if (is_cxl_root(port)) return NULL; - if (dev_is_pci(port->uport)) { - struct pci_dev *pdev = to_pci_dev(port->uport); + if (dev_is_pci(port->uport_dev)) { + struct pci_dev *pdev = to_pci_dev(port->uport_dev); return pdev->subordinate; } - return xa_load(&cxl_root_buses, (unsigned long)port->uport); + return xa_load(&cxl_root_buses, (unsigned long)port->uport_dev); } EXPORT_SYMBOL_NS_GPL(cxl_port_to_pci_bus, CXL); -static void unregister_pci_bus(void *uport) +static void unregister_pci_bus(void *uport_dev) { - xa_erase(&cxl_root_buses, (unsigned long)uport); + xa_erase(&cxl_root_buses, (unsigned long)uport_dev); } -int devm_cxl_register_pci_bus(struct device *host, struct device *uport, +int devm_cxl_register_pci_bus(struct device *host, struct device *uport_dev, struct pci_bus *bus) { int rc; - if (dev_is_pci(uport)) + if (dev_is_pci(uport_dev)) return -EINVAL; - rc = xa_insert(&cxl_root_buses, (unsigned long)uport, bus, GFP_KERNEL); + rc = xa_insert(&cxl_root_buses, (unsigned long)uport_dev, bus, + GFP_KERNEL); if (rc) return rc; - return devm_add_action_or_reset(host, unregister_pci_bus, uport); + return devm_add_action_or_reset(host, unregister_pci_bus, uport_dev); } EXPORT_SYMBOL_NS_GPL(devm_cxl_register_pci_bus, CXL); @@ -920,7 +924,7 @@ __devm_cxl_add_dport(struct cxl_port *port, struct device *dport_dev, int rc; if (is_cxl_root(port)) - host = port->uport; + host = port->uport_dev; else host = &port->dev; @@ -1374,7 +1378,7 @@ static int add_port_attach_ep(struct cxl_memdev *cxlmd, rc = PTR_ERR(port); else { dev_dbg(&cxlmd->dev, "add to new port %s:%s\n", - dev_name(&port->dev), dev_name(port->uport)); + dev_name(&port->dev), dev_name(port->uport_dev)); rc = cxl_add_ep(dport, &cxlmd->dev); if (rc == -EBUSY) { /* @@ -1436,7 +1440,8 @@ int devm_cxl_enumerate_ports(struct cxl_memdev *cxlmd) if (port) { dev_dbg(&cxlmd->dev, "found already registered port %s:%s\n", - dev_name(&port->dev), dev_name(port->uport)); + dev_name(&port->dev), + dev_name(port->uport_dev)); rc = cxl_add_ep(dport, &cxlmd->dev); /* diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c index 13cda989d944..39825e5301d0 100644 --- a/drivers/cxl/core/region.c +++ b/drivers/cxl/core/region.c @@ -906,10 +906,10 @@ static int cxl_port_attach_region(struct cxl_port *port, dev_dbg(&cxlr->dev, "%s:%s %s add: %s:%s @ %d next: %s nr_eps: %d nr_targets: %d\n", - dev_name(port->uport), dev_name(&port->dev), + dev_name(port->uport_dev), dev_name(&port->dev), dev_name(&cxld->dev), dev_name(&cxlmd->dev), dev_name(&cxled->cxld.dev), pos, - ep ? ep->next ? dev_name(ep->next->uport) : + ep ? ep->next ? dev_name(ep->next->uport_dev) : dev_name(&cxlmd->dev) : "none", cxl_rr->nr_eps, cxl_rr->nr_targets); @@ -984,7 +984,7 @@ static int check_last_peer(struct cxl_endpoint_decoder *cxled, */ if (pos < distance) { dev_dbg(&cxlr->dev, "%s:%s: cannot host %s:%s at %d\n", - dev_name(port->uport), dev_name(&port->dev), + dev_name(port->uport_dev), dev_name(&port->dev), dev_name(&cxlmd->dev), dev_name(&cxled->cxld.dev), pos); return -ENXIO; } @@ -994,7 +994,7 @@ static int check_last_peer(struct cxl_endpoint_decoder *cxled, if (ep->dport != ep_peer->dport) { dev_dbg(&cxlr->dev, "%s:%s: %s:%s pos %d mismatched peer %s:%s\n", - dev_name(port->uport), dev_name(&port->dev), + dev_name(port->uport_dev), dev_name(&port->dev), dev_name(&cxlmd->dev), dev_name(&cxled->cxld.dev), pos, dev_name(&cxlmd_peer->dev), dev_name(&cxled_peer->cxld.dev)); @@ -1026,7 +1026,7 @@ static int cxl_port_setup_targets(struct cxl_port *port, */ if (!is_power_of_2(cxl_rr->nr_targets)) { dev_dbg(&cxlr->dev, "%s:%s: invalid target count %d\n", - dev_name(port->uport), dev_name(&port->dev), + dev_name(port->uport_dev), dev_name(&port->dev), cxl_rr->nr_targets); return -EINVAL; } @@ -1076,7 +1076,7 @@ static int cxl_port_setup_targets(struct cxl_port *port, rc = granularity_to_eig(parent_ig, &peig); if (rc) { dev_dbg(&cxlr->dev, "%s:%s: invalid parent granularity: %d\n", - dev_name(parent_port->uport), + dev_name(parent_port->uport_dev), dev_name(&parent_port->dev), parent_ig); return rc; } @@ -1084,7 +1084,7 @@ static int cxl_port_setup_targets(struct cxl_port *port, rc = ways_to_eiw(parent_iw, &peiw); if (rc) { dev_dbg(&cxlr->dev, "%s:%s: invalid parent interleave: %d\n", - dev_name(parent_port->uport), + dev_name(parent_port->uport_dev), dev_name(&parent_port->dev), parent_iw); return rc; } @@ -1093,7 +1093,7 @@ static int cxl_port_setup_targets(struct cxl_port *port, rc = ways_to_eiw(iw, &eiw); if (rc) { dev_dbg(&cxlr->dev, "%s:%s: invalid port interleave: %d\n", - dev_name(port->uport), dev_name(&port->dev), iw); + dev_name(port->uport_dev), dev_name(&port->dev), iw); return rc; } @@ -1113,7 +1113,7 @@ static int cxl_port_setup_targets(struct cxl_port *port, rc = eig_to_granularity(eig, &ig); if (rc) { dev_dbg(&cxlr->dev, "%s:%s: invalid interleave: %d\n", - dev_name(port->uport), dev_name(&port->dev), + dev_name(port->uport_dev), dev_name(&port->dev), 256 << eig); return rc; } @@ -1126,11 +1126,11 @@ static int cxl_port_setup_targets(struct cxl_port *port, ((cxld->flags & CXL_DECODER_F_ENABLE) == 0)) { dev_err(&cxlr->dev, "%s:%s %s expected iw: %d ig: %d %pr\n", - dev_name(port->uport), dev_name(&port->dev), + dev_name(port->uport_dev), dev_name(&port->dev), __func__, iw, ig, p->res); dev_err(&cxlr->dev, "%s:%s %s got iw: %d ig: %d state: %s %#llx:%#llx\n", - dev_name(port->uport), dev_name(&port->dev), + dev_name(port->uport_dev), dev_name(&port->dev), __func__, cxld->interleave_ways, cxld->interleave_granularity, (cxld->flags & CXL_DECODER_F_ENABLE) ? @@ -1147,20 +1147,20 @@ static int cxl_port_setup_targets(struct cxl_port *port, .end = p->res->end, }; } - dev_dbg(&cxlr->dev, "%s:%s iw: %d ig: %d\n", dev_name(port->uport), + dev_dbg(&cxlr->dev, "%s:%s iw: %d ig: %d\n", dev_name(port->uport_dev), dev_name(&port->dev), iw, ig); add_target: if (cxl_rr->nr_targets_set == cxl_rr->nr_targets) { dev_dbg(&cxlr->dev, "%s:%s: targets full trying to add %s:%s at %d\n", - dev_name(port->uport), dev_name(&port->dev), + dev_name(port->uport_dev), dev_name(&port->dev), dev_name(&cxlmd->dev), dev_name(&cxled->cxld.dev), pos); return -ENXIO; } if (test_bit(CXL_REGION_F_AUTO, &cxlr->flags)) { if (cxlsd->target[cxl_rr->nr_targets_set] != ep->dport) { dev_dbg(&cxlr->dev, "%s:%s: %s expected %s at %d\n", - dev_name(port->uport), dev_name(&port->dev), + dev_name(port->uport_dev), dev_name(&port->dev), dev_name(&cxlsd->cxld.dev), dev_name(ep->dport->dport_dev), cxl_rr->nr_targets_set); @@ -1172,7 +1172,7 @@ static int cxl_port_setup_targets(struct cxl_port *port, out_target_set: cxl_rr->nr_targets_set += inc; dev_dbg(&cxlr->dev, "%s:%s target[%d] = %s for %s:%s @ %d\n", - dev_name(port->uport), dev_name(&port->dev), + dev_name(port->uport_dev), dev_name(&port->dev), cxl_rr->nr_targets_set - 1, dev_name(ep->dport->dport_dev), dev_name(&cxlmd->dev), dev_name(&cxled->cxld.dev), pos); @@ -1492,7 +1492,7 @@ static int cmp_decode_pos(const void *a, const void *b) if (!dev) { struct range *range = &cxled_a->cxld.hpa_range; - dev_err(port->uport, + dev_err(port->uport_dev, "failed to find decoder that maps %#llx-%#llx\n", range->start, range->end); goto err; @@ -1507,14 +1507,15 @@ static int cmp_decode_pos(const void *a, const void *b) put_device(dev); if (a_pos < 0 || b_pos < 0) { - dev_err(port->uport, + dev_err(port->uport_dev, "failed to find shared decoder for %s and %s\n", dev_name(cxlmd_a->dev.parent), dev_name(cxlmd_b->dev.parent)); goto err; } - dev_dbg(port->uport, "%s comes %s %s\n", dev_name(cxlmd_a->dev.parent), + dev_dbg(port->uport_dev, "%s comes %s %s\n", + dev_name(cxlmd_a->dev.parent), a_pos - b_pos < 0 ? "before" : "after", dev_name(cxlmd_b->dev.parent)); @@ -2059,11 +2060,11 @@ static struct cxl_region *devm_cxl_add_region(struct cxl_root_decoder *cxlrd, if (rc) goto err; - rc = devm_add_action_or_reset(port->uport, unregister_region, cxlr); + rc = devm_add_action_or_reset(port->uport_dev, unregister_region, cxlr); if (rc) return ERR_PTR(rc); - dev_dbg(port->uport, "%s: created %s\n", + dev_dbg(port->uport_dev, "%s: created %s\n", dev_name(&cxlrd->cxlsd.cxld.dev), dev_name(dev)); return cxlr; @@ -2191,7 +2192,7 @@ static ssize_t delete_region_store(struct device *dev, if (IS_ERR(cxlr)) return PTR_ERR(cxlr); - devm_release_action(port->uport, unregister_region, cxlr); + devm_release_action(port->uport_dev, unregister_region, cxlr); put_device(&cxlr->dev); return len; @@ -2356,7 +2357,8 @@ int cxl_get_poison_by_endpoint(struct cxl_port *port) rc = device_for_each_child(&port->dev, &ctx, poison_by_decoder); if (rc == 1) - rc = cxl_get_poison_unmapped(to_cxl_memdev(port->uport), &ctx); + rc = cxl_get_poison_unmapped(to_cxl_memdev(port->uport_dev), + &ctx); up_read(&cxl_region_rwsem); return rc; @@ -2732,7 +2734,7 @@ static struct cxl_region *construct_region(struct cxl_root_decoder *cxlrd, err: up_write(&cxl_region_rwsem); - devm_release_action(port->uport, unregister_region, cxlr); + devm_release_action(port->uport_dev, unregister_region, cxlr); return ERR_PTR(rc); } diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index 7232c2a0e27c..754cfe59ae37 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -536,7 +536,7 @@ struct cxl_dax_region { * downstream port devices to construct a CXL memory * decode hierarchy. * @dev: this port's device - * @uport: PCI or platform device implementing the upstream port capability + * @uport_dev: PCI or platform device implementing the upstream port capability * @host_bridge: Shortcut to the platform attach point for this port * @id: id for port device-name * @dports: cxl_dport instances referenced by decoders @@ -555,7 +555,7 @@ struct cxl_dax_region { */ struct cxl_port { struct device dev; - struct device *uport; + struct device *uport_dev; struct device *host_bridge; int id; struct xarray dports; @@ -641,21 +641,22 @@ struct cxl_region_ref { /* * The platform firmware device hosting the root is also the top of the * CXL port topology. All other CXL ports have another CXL port as their - * parent and their ->uport / host device is out-of-line of the port + * parent and their ->uport_dev / host device is out-of-line of the port * ancestry. */ static inline bool is_cxl_root(struct cxl_port *port) { - return port->uport == port->dev.parent; + return port->uport_dev == port->dev.parent; } bool is_cxl_port(const struct device *dev); struct cxl_port *to_cxl_port(const struct device *dev); struct pci_bus; -int devm_cxl_register_pci_bus(struct device *host, struct device *uport, +int devm_cxl_register_pci_bus(struct device *host, struct device *uport_dev, struct pci_bus *bus); struct pci_bus *cxl_port_to_pci_bus(struct cxl_port *port); -struct cxl_port *devm_cxl_add_port(struct device *host, struct device *uport, +struct cxl_port *devm_cxl_add_port(struct device *host, + struct device *uport_dev, resource_size_t component_reg_phys, struct cxl_dport *parent_dport); struct cxl_port *find_cxl_root(struct cxl_port *port); diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h index a2845a7a69d8..76743016b64c 100644 --- a/drivers/cxl/cxlmem.h +++ b/drivers/cxl/cxlmem.h @@ -72,13 +72,13 @@ cxled_to_memdev(struct cxl_endpoint_decoder *cxled) { struct cxl_port *port = to_cxl_port(cxled->cxld.dev.parent); - return to_cxl_memdev(port->uport); + return to_cxl_memdev(port->uport_dev); } bool is_cxl_memdev(const struct device *dev); static inline bool is_cxl_endpoint(struct cxl_port *port) { - return is_cxl_memdev(port->uport); + return is_cxl_memdev(port->uport_dev); } struct cxl_memdev *devm_cxl_add_memdev(struct cxl_dev_state *cxlds); diff --git a/drivers/cxl/mem.c b/drivers/cxl/mem.c index 45d4c32d78b0..4cc461c22b8b 100644 --- a/drivers/cxl/mem.c +++ b/drivers/cxl/mem.c @@ -163,7 +163,7 @@ static int cxl_mem_probe(struct device *dev) } if (dport->rch) - endpoint_parent = parent_port->uport; + endpoint_parent = parent_port->uport_dev; else endpoint_parent = &parent_port->dev; diff --git a/drivers/cxl/port.c b/drivers/cxl/port.c index c23b6164e1c0..4cef2bf45ad2 100644 --- a/drivers/cxl/port.c +++ b/drivers/cxl/port.c @@ -91,7 +91,7 @@ static int cxl_switch_port_probe(struct cxl_port *port) static int cxl_endpoint_port_probe(struct cxl_port *port) { struct cxl_endpoint_dvsec_info info = { .port = port }; - struct cxl_memdev *cxlmd = to_cxl_memdev(port->uport); + struct cxl_memdev *cxlmd = to_cxl_memdev(port->uport_dev); struct cxl_dev_state *cxlds = cxlmd->cxlds; struct cxl_hdm *cxlhdm; struct cxl_port *root; diff --git a/tools/testing/cxl/test/cxl.c b/tools/testing/cxl/test/cxl.c index f5c04787bcc8..4f62eb55f8b8 100644 --- a/tools/testing/cxl/test/cxl.c +++ b/tools/testing/cxl/test/cxl.c @@ -754,7 +754,7 @@ static void mock_init_hdm_decoder(struct cxl_decoder *cxld) /* check is endpoint is attach to host-bridge0 */ port = cxled_to_port(cxled); do { - if (port->uport == &cxl_host_bridge[0]->dev) { + if (port->uport_dev == &cxl_host_bridge[0]->dev) { hb0 = true; break; } @@ -889,7 +889,7 @@ static int mock_cxl_enumerate_decoders(struct cxl_hdm *cxlhdm, mock_init_hdm_decoder(cxld); if (target_count) { - rc = device_for_each_child(port->uport, &ctx, + rc = device_for_each_child(port->uport_dev, &ctx, map_targets); if (rc) { put_device(&cxld->dev); @@ -919,29 +919,29 @@ static int mock_cxl_port_enumerate_dports(struct cxl_port *port) int i, array_size; if (port->depth == 1) { - if (is_multi_bridge(port->uport)) { + if (is_multi_bridge(port->uport_dev)) { array_size = ARRAY_SIZE(cxl_root_port); array = cxl_root_port; - } else if (is_single_bridge(port->uport)) { + } else if (is_single_bridge(port->uport_dev)) { array_size = ARRAY_SIZE(cxl_root_single); array = cxl_root_single; } else { dev_dbg(&port->dev, "%s: unknown bridge type\n", - dev_name(port->uport)); + dev_name(port->uport_dev)); return -ENXIO; } } else if (port->depth == 2) { struct cxl_port *parent = to_cxl_port(port->dev.parent); - if (is_multi_bridge(parent->uport)) { + if (is_multi_bridge(parent->uport_dev)) { array_size = ARRAY_SIZE(cxl_switch_dport); array = cxl_switch_dport; - } else if (is_single_bridge(parent->uport)) { + } else if (is_single_bridge(parent->uport_dev)) { array_size = ARRAY_SIZE(cxl_swd_single); array = cxl_swd_single; } else { dev_dbg(&port->dev, "%s: unknown bridge type\n", - dev_name(port->uport)); + dev_name(port->uport_dev)); return -ENXIO; } } else { @@ -954,9 +954,9 @@ static int mock_cxl_port_enumerate_dports(struct cxl_port *port) struct platform_device *pdev = array[i]; struct cxl_dport *dport; - if (pdev->dev.parent != port->uport) { + if (pdev->dev.parent != port->uport_dev) { dev_dbg(&port->dev, "%s: mismatch parent %s\n", - dev_name(port->uport), + dev_name(port->uport_dev), dev_name(pdev->dev.parent)); continue; } diff --git a/tools/testing/cxl/test/mock.c b/tools/testing/cxl/test/mock.c index dbeef5c6f606..da554df50bac 100644 --- a/tools/testing/cxl/test/mock.c +++ b/tools/testing/cxl/test/mock.c @@ -139,7 +139,7 @@ struct cxl_hdm *__wrap_devm_cxl_setup_hdm(struct cxl_port *port, struct cxl_hdm *cxlhdm; struct cxl_mock_ops *ops = get_cxl_mock_ops(&index); - if (ops && ops->is_mock_port(port->uport)) + if (ops && ops->is_mock_port(port->uport_dev)) cxlhdm = ops->devm_cxl_setup_hdm(port, info); else cxlhdm = devm_cxl_setup_hdm(port, info); @@ -154,7 +154,7 @@ int __wrap_devm_cxl_enable_hdm(struct cxl_port *port, struct cxl_hdm *cxlhdm) int index, rc; struct cxl_mock_ops *ops = get_cxl_mock_ops(&index); - if (ops && ops->is_mock_port(port->uport)) + if (ops && ops->is_mock_port(port->uport_dev)) rc = 0; else rc = devm_cxl_enable_hdm(port, cxlhdm); @@ -169,7 +169,7 @@ int __wrap_devm_cxl_add_passthrough_decoder(struct cxl_port *port) int rc, index; struct cxl_mock_ops *ops = get_cxl_mock_ops(&index); - if (ops && ops->is_mock_port(port->uport)) + if (ops && ops->is_mock_port(port->uport_dev)) rc = ops->devm_cxl_add_passthrough_decoder(port); else rc = devm_cxl_add_passthrough_decoder(port); @@ -186,7 +186,7 @@ int __wrap_devm_cxl_enumerate_decoders(struct cxl_hdm *cxlhdm, struct cxl_port *port = cxlhdm->port; struct cxl_mock_ops *ops = get_cxl_mock_ops(&index); - if (ops && ops->is_mock_port(port->uport)) + if (ops && ops->is_mock_port(port->uport_dev)) rc = ops->devm_cxl_enumerate_decoders(cxlhdm, info); else rc = devm_cxl_enumerate_decoders(cxlhdm, info); @@ -201,7 +201,7 @@ int __wrap_devm_cxl_port_enumerate_dports(struct cxl_port *port) int rc, index; struct cxl_mock_ops *ops = get_cxl_mock_ops(&index); - if (ops && ops->is_mock_port(port->uport)) + if (ops && ops->is_mock_port(port->uport_dev)) rc = ops->devm_cxl_port_enumerate_dports(port); else rc = devm_cxl_port_enumerate_dports(port);
On 6/8/23 14:08, Dan Williams wrote: > Terry Bowman wrote: >> Hi Dan, >> >> >> On 6/8/23 01:42, Dan Williams wrote: >>> Terry Bowman wrote: >>>> From: Robert Richter <rrichter@amd.com> >>>> >>>> Reading code like dport->dport does not immediately suggest that this >>>> points to the corresponding device structure of the dport. Rename >>>> struct member @dport to @dev. >>> >>> This one I don't agree with. >>> >>> This can switch to ->dport_dev if you like. The reason for ->dport was >>> for symmetry with the ->uport of a 'struct cxl_port'. So if you change >>> this to ->dport_dev then also make the ->uport_dev change for symmetry. >>> >>> Unlike a 'struct cxl_port' a 'struct cxl_dport' is not a device in its >>> own right which is what I see when I read dport->dev. >>> >> >> Ok, I'll change the structure member names and code to use the following: >> struct cxl_dport::dev -> struct cxl_dport::dport_dev >> >> struct cxl_port::uport -> struct cxl_port::uport_dev > > Sounds good, to save duplication of work I already have this that you > can just adopt: Thanks Dan. I'll insert your patch into the series. Regards, Terry > > -- >8 -- > Subject: cxl: Rename 'uport' to 'uport_dev' > > From: Dan Williams <dan.j.williams@intel.com> > > For symmetry with the recent rename of ->dport_dev for a 'struct > cxl_dport', add the "_dev" suffix to the ->uport property of a 'struct > cxl_port'. These devices represent the downstream-port-device and > upstream-port-device respectively in the CXL/PCIe topology. > > Signed-off-by: Dan Williams <dan.j.williams@intel.com> > --- > drivers/cxl/core/pci.c | 4 +-- > drivers/cxl/core/port.c | 61 ++++++++++++++++++++++------------------- > drivers/cxl/core/region.c | 48 +++++++++++++++++--------------- > drivers/cxl/cxl.h | 13 +++++---- > drivers/cxl/cxlmem.h | 4 +-- > drivers/cxl/mem.c | 2 + > drivers/cxl/port.c | 2 + > tools/testing/cxl/test/cxl.c | 20 +++++++------ > tools/testing/cxl/test/mock.c | 10 +++---- > 9 files changed, 86 insertions(+), 78 deletions(-) > > diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c > index 67f4ab6daa34..375f01c6cad6 100644 > --- a/drivers/cxl/core/pci.c > +++ b/drivers/cxl/core/pci.c > @@ -67,7 +67,7 @@ static int match_add_dports(struct pci_dev *pdev, void *data) > > /** > * devm_cxl_port_enumerate_dports - enumerate downstream ports of the upstream port > - * @port: cxl_port whose ->uport is the upstream of dports to be enumerated > + * @port: cxl_port whose ->uport_dev is the upstream of dports to be enumerated > * > * Returns a positive number of dports enumerated or a negative error > * code. > @@ -622,7 +622,7 @@ static int cxl_cdat_read_table(struct device *dev, > */ > void read_cdat_data(struct cxl_port *port) > { > - struct cxl_memdev *cxlmd = to_cxl_memdev(port->uport); > + struct cxl_memdev *cxlmd = to_cxl_memdev(port->uport_dev); > struct device *host = cxlmd->dev.parent; > struct device *dev = &port->dev; > struct pci_doe_mb *cdat_doe; > diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c > index 93800e6e095f..a45a063d52ce 100644 > --- a/drivers/cxl/core/port.c > +++ b/drivers/cxl/core/port.c > @@ -561,9 +561,9 @@ static void unregister_port(void *_port) > * unregistered while holding their parent port lock. > */ > if (!parent) > - lock_dev = port->uport; > + lock_dev = port->uport_dev; > else if (is_cxl_root(parent)) > - lock_dev = parent->uport; > + lock_dev = parent->uport_dev; > else > lock_dev = &parent->dev; > > @@ -583,7 +583,8 @@ static int devm_cxl_link_uport(struct device *host, struct cxl_port *port) > { > int rc; > > - rc = sysfs_create_link(&port->dev.kobj, &port->uport->kobj, "uport"); > + rc = sysfs_create_link(&port->dev.kobj, &port->uport_dev->kobj, > + "uport"); > if (rc) > return rc; > return devm_add_action_or_reset(host, cxl_unlink_uport, port); > @@ -614,7 +615,7 @@ static int devm_cxl_link_parent_dport(struct device *host, > > static struct lock_class_key cxl_port_key; > > -static struct cxl_port *cxl_port_alloc(struct device *uport, > +static struct cxl_port *cxl_port_alloc(struct device *uport_dev, > resource_size_t component_reg_phys, > struct cxl_dport *parent_dport) > { > @@ -630,7 +631,7 @@ static struct cxl_port *cxl_port_alloc(struct device *uport, > if (rc < 0) > goto err; > port->id = rc; > - port->uport = uport; > + port->uport_dev = uport_dev; > > /* > * The top-level cxl_port "cxl_root" does not have a cxl_port as > @@ -660,10 +661,11 @@ static struct cxl_port *cxl_port_alloc(struct device *uport, > else if (parent_dport->rch) > port->host_bridge = parent_dport->dport_dev; > else > - port->host_bridge = iter->uport; > - dev_dbg(uport, "host-bridge: %s\n", dev_name(port->host_bridge)); > + port->host_bridge = iter->uport_dev; > + dev_dbg(uport_dev, "host-bridge: %s\n", > + dev_name(port->host_bridge)); > } else > - dev->parent = uport; > + dev->parent = uport_dev; > > port->component_reg_phys = component_reg_phys; > ida_init(&port->decoder_ida); > @@ -687,7 +689,7 @@ static struct cxl_port *cxl_port_alloc(struct device *uport, > } > > static struct cxl_port *__devm_cxl_add_port(struct device *host, > - struct device *uport, > + struct device *uport_dev, > resource_size_t component_reg_phys, > struct cxl_dport *parent_dport) > { > @@ -695,12 +697,12 @@ static struct cxl_port *__devm_cxl_add_port(struct device *host, > struct device *dev; > int rc; > > - port = cxl_port_alloc(uport, component_reg_phys, parent_dport); > + port = cxl_port_alloc(uport_dev, component_reg_phys, parent_dport); > if (IS_ERR(port)) > return port; > > dev = &port->dev; > - if (is_cxl_memdev(uport)) > + if (is_cxl_memdev(uport_dev)) > rc = dev_set_name(dev, "endpoint%d", port->id); > else if (parent_dport) > rc = dev_set_name(dev, "port%d", port->id); > @@ -735,28 +737,29 @@ static struct cxl_port *__devm_cxl_add_port(struct device *host, > /** > * devm_cxl_add_port - register a cxl_port in CXL memory decode hierarchy > * @host: host device for devm operations > - * @uport: "physical" device implementing this upstream port > + * @uport_dev: "physical" device implementing this upstream port > * @component_reg_phys: (optional) for configurable cxl_port instances > * @parent_dport: next hop up in the CXL memory decode hierarchy > */ > -struct cxl_port *devm_cxl_add_port(struct device *host, struct device *uport, > +struct cxl_port *devm_cxl_add_port(struct device *host, > + struct device *uport_dev, > resource_size_t component_reg_phys, > struct cxl_dport *parent_dport) > { > struct cxl_port *port, *parent_port; > > - port = __devm_cxl_add_port(host, uport, component_reg_phys, > + port = __devm_cxl_add_port(host, uport_dev, component_reg_phys, > parent_dport); > > parent_port = parent_dport ? parent_dport->port : NULL; > if (IS_ERR(port)) { > - dev_dbg(uport, "Failed to add%s%s%s: %ld\n", > + dev_dbg(uport_dev, "Failed to add%s%s%s: %ld\n", > parent_port ? " port to " : "", > parent_port ? dev_name(&parent_port->dev) : "", > parent_port ? "" : " root port", > PTR_ERR(port)); > } else { > - dev_dbg(uport, "%s added%s%s%s\n", > + dev_dbg(uport_dev, "%s added%s%s%s\n", > dev_name(&port->dev), > parent_port ? " to " : "", > parent_port ? dev_name(&parent_port->dev) : "", > @@ -773,33 +776,34 @@ struct pci_bus *cxl_port_to_pci_bus(struct cxl_port *port) > if (is_cxl_root(port)) > return NULL; > > - if (dev_is_pci(port->uport)) { > - struct pci_dev *pdev = to_pci_dev(port->uport); > + if (dev_is_pci(port->uport_dev)) { > + struct pci_dev *pdev = to_pci_dev(port->uport_dev); > > return pdev->subordinate; > } > > - return xa_load(&cxl_root_buses, (unsigned long)port->uport); > + return xa_load(&cxl_root_buses, (unsigned long)port->uport_dev); > } > EXPORT_SYMBOL_NS_GPL(cxl_port_to_pci_bus, CXL); > > -static void unregister_pci_bus(void *uport) > +static void unregister_pci_bus(void *uport_dev) > { > - xa_erase(&cxl_root_buses, (unsigned long)uport); > + xa_erase(&cxl_root_buses, (unsigned long)uport_dev); > } > > -int devm_cxl_register_pci_bus(struct device *host, struct device *uport, > +int devm_cxl_register_pci_bus(struct device *host, struct device *uport_dev, > struct pci_bus *bus) > { > int rc; > > - if (dev_is_pci(uport)) > + if (dev_is_pci(uport_dev)) > return -EINVAL; > > - rc = xa_insert(&cxl_root_buses, (unsigned long)uport, bus, GFP_KERNEL); > + rc = xa_insert(&cxl_root_buses, (unsigned long)uport_dev, bus, > + GFP_KERNEL); > if (rc) > return rc; > - return devm_add_action_or_reset(host, unregister_pci_bus, uport); > + return devm_add_action_or_reset(host, unregister_pci_bus, uport_dev); > } > EXPORT_SYMBOL_NS_GPL(devm_cxl_register_pci_bus, CXL); > > @@ -920,7 +924,7 @@ __devm_cxl_add_dport(struct cxl_port *port, struct device *dport_dev, > int rc; > > if (is_cxl_root(port)) > - host = port->uport; > + host = port->uport_dev; > else > host = &port->dev; > > @@ -1374,7 +1378,7 @@ static int add_port_attach_ep(struct cxl_memdev *cxlmd, > rc = PTR_ERR(port); > else { > dev_dbg(&cxlmd->dev, "add to new port %s:%s\n", > - dev_name(&port->dev), dev_name(port->uport)); > + dev_name(&port->dev), dev_name(port->uport_dev)); > rc = cxl_add_ep(dport, &cxlmd->dev); > if (rc == -EBUSY) { > /* > @@ -1436,7 +1440,8 @@ int devm_cxl_enumerate_ports(struct cxl_memdev *cxlmd) > if (port) { > dev_dbg(&cxlmd->dev, > "found already registered port %s:%s\n", > - dev_name(&port->dev), dev_name(port->uport)); > + dev_name(&port->dev), > + dev_name(port->uport_dev)); > rc = cxl_add_ep(dport, &cxlmd->dev); > > /* > diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c > index 13cda989d944..39825e5301d0 100644 > --- a/drivers/cxl/core/region.c > +++ b/drivers/cxl/core/region.c > @@ -906,10 +906,10 @@ static int cxl_port_attach_region(struct cxl_port *port, > > dev_dbg(&cxlr->dev, > "%s:%s %s add: %s:%s @ %d next: %s nr_eps: %d nr_targets: %d\n", > - dev_name(port->uport), dev_name(&port->dev), > + dev_name(port->uport_dev), dev_name(&port->dev), > dev_name(&cxld->dev), dev_name(&cxlmd->dev), > dev_name(&cxled->cxld.dev), pos, > - ep ? ep->next ? dev_name(ep->next->uport) : > + ep ? ep->next ? dev_name(ep->next->uport_dev) : > dev_name(&cxlmd->dev) : > "none", > cxl_rr->nr_eps, cxl_rr->nr_targets); > @@ -984,7 +984,7 @@ static int check_last_peer(struct cxl_endpoint_decoder *cxled, > */ > if (pos < distance) { > dev_dbg(&cxlr->dev, "%s:%s: cannot host %s:%s at %d\n", > - dev_name(port->uport), dev_name(&port->dev), > + dev_name(port->uport_dev), dev_name(&port->dev), > dev_name(&cxlmd->dev), dev_name(&cxled->cxld.dev), pos); > return -ENXIO; > } > @@ -994,7 +994,7 @@ static int check_last_peer(struct cxl_endpoint_decoder *cxled, > if (ep->dport != ep_peer->dport) { > dev_dbg(&cxlr->dev, > "%s:%s: %s:%s pos %d mismatched peer %s:%s\n", > - dev_name(port->uport), dev_name(&port->dev), > + dev_name(port->uport_dev), dev_name(&port->dev), > dev_name(&cxlmd->dev), dev_name(&cxled->cxld.dev), pos, > dev_name(&cxlmd_peer->dev), > dev_name(&cxled_peer->cxld.dev)); > @@ -1026,7 +1026,7 @@ static int cxl_port_setup_targets(struct cxl_port *port, > */ > if (!is_power_of_2(cxl_rr->nr_targets)) { > dev_dbg(&cxlr->dev, "%s:%s: invalid target count %d\n", > - dev_name(port->uport), dev_name(&port->dev), > + dev_name(port->uport_dev), dev_name(&port->dev), > cxl_rr->nr_targets); > return -EINVAL; > } > @@ -1076,7 +1076,7 @@ static int cxl_port_setup_targets(struct cxl_port *port, > rc = granularity_to_eig(parent_ig, &peig); > if (rc) { > dev_dbg(&cxlr->dev, "%s:%s: invalid parent granularity: %d\n", > - dev_name(parent_port->uport), > + dev_name(parent_port->uport_dev), > dev_name(&parent_port->dev), parent_ig); > return rc; > } > @@ -1084,7 +1084,7 @@ static int cxl_port_setup_targets(struct cxl_port *port, > rc = ways_to_eiw(parent_iw, &peiw); > if (rc) { > dev_dbg(&cxlr->dev, "%s:%s: invalid parent interleave: %d\n", > - dev_name(parent_port->uport), > + dev_name(parent_port->uport_dev), > dev_name(&parent_port->dev), parent_iw); > return rc; > } > @@ -1093,7 +1093,7 @@ static int cxl_port_setup_targets(struct cxl_port *port, > rc = ways_to_eiw(iw, &eiw); > if (rc) { > dev_dbg(&cxlr->dev, "%s:%s: invalid port interleave: %d\n", > - dev_name(port->uport), dev_name(&port->dev), iw); > + dev_name(port->uport_dev), dev_name(&port->dev), iw); > return rc; > } > > @@ -1113,7 +1113,7 @@ static int cxl_port_setup_targets(struct cxl_port *port, > rc = eig_to_granularity(eig, &ig); > if (rc) { > dev_dbg(&cxlr->dev, "%s:%s: invalid interleave: %d\n", > - dev_name(port->uport), dev_name(&port->dev), > + dev_name(port->uport_dev), dev_name(&port->dev), > 256 << eig); > return rc; > } > @@ -1126,11 +1126,11 @@ static int cxl_port_setup_targets(struct cxl_port *port, > ((cxld->flags & CXL_DECODER_F_ENABLE) == 0)) { > dev_err(&cxlr->dev, > "%s:%s %s expected iw: %d ig: %d %pr\n", > - dev_name(port->uport), dev_name(&port->dev), > + dev_name(port->uport_dev), dev_name(&port->dev), > __func__, iw, ig, p->res); > dev_err(&cxlr->dev, > "%s:%s %s got iw: %d ig: %d state: %s %#llx:%#llx\n", > - dev_name(port->uport), dev_name(&port->dev), > + dev_name(port->uport_dev), dev_name(&port->dev), > __func__, cxld->interleave_ways, > cxld->interleave_granularity, > (cxld->flags & CXL_DECODER_F_ENABLE) ? > @@ -1147,20 +1147,20 @@ static int cxl_port_setup_targets(struct cxl_port *port, > .end = p->res->end, > }; > } > - dev_dbg(&cxlr->dev, "%s:%s iw: %d ig: %d\n", dev_name(port->uport), > + dev_dbg(&cxlr->dev, "%s:%s iw: %d ig: %d\n", dev_name(port->uport_dev), > dev_name(&port->dev), iw, ig); > add_target: > if (cxl_rr->nr_targets_set == cxl_rr->nr_targets) { > dev_dbg(&cxlr->dev, > "%s:%s: targets full trying to add %s:%s at %d\n", > - dev_name(port->uport), dev_name(&port->dev), > + dev_name(port->uport_dev), dev_name(&port->dev), > dev_name(&cxlmd->dev), dev_name(&cxled->cxld.dev), pos); > return -ENXIO; > } > if (test_bit(CXL_REGION_F_AUTO, &cxlr->flags)) { > if (cxlsd->target[cxl_rr->nr_targets_set] != ep->dport) { > dev_dbg(&cxlr->dev, "%s:%s: %s expected %s at %d\n", > - dev_name(port->uport), dev_name(&port->dev), > + dev_name(port->uport_dev), dev_name(&port->dev), > dev_name(&cxlsd->cxld.dev), > dev_name(ep->dport->dport_dev), > cxl_rr->nr_targets_set); > @@ -1172,7 +1172,7 @@ static int cxl_port_setup_targets(struct cxl_port *port, > out_target_set: > cxl_rr->nr_targets_set += inc; > dev_dbg(&cxlr->dev, "%s:%s target[%d] = %s for %s:%s @ %d\n", > - dev_name(port->uport), dev_name(&port->dev), > + dev_name(port->uport_dev), dev_name(&port->dev), > cxl_rr->nr_targets_set - 1, dev_name(ep->dport->dport_dev), > dev_name(&cxlmd->dev), dev_name(&cxled->cxld.dev), pos); > > @@ -1492,7 +1492,7 @@ static int cmp_decode_pos(const void *a, const void *b) > if (!dev) { > struct range *range = &cxled_a->cxld.hpa_range; > > - dev_err(port->uport, > + dev_err(port->uport_dev, > "failed to find decoder that maps %#llx-%#llx\n", > range->start, range->end); > goto err; > @@ -1507,14 +1507,15 @@ static int cmp_decode_pos(const void *a, const void *b) > put_device(dev); > > if (a_pos < 0 || b_pos < 0) { > - dev_err(port->uport, > + dev_err(port->uport_dev, > "failed to find shared decoder for %s and %s\n", > dev_name(cxlmd_a->dev.parent), > dev_name(cxlmd_b->dev.parent)); > goto err; > } > > - dev_dbg(port->uport, "%s comes %s %s\n", dev_name(cxlmd_a->dev.parent), > + dev_dbg(port->uport_dev, "%s comes %s %s\n", > + dev_name(cxlmd_a->dev.parent), > a_pos - b_pos < 0 ? "before" : "after", > dev_name(cxlmd_b->dev.parent)); > > @@ -2059,11 +2060,11 @@ static struct cxl_region *devm_cxl_add_region(struct cxl_root_decoder *cxlrd, > if (rc) > goto err; > > - rc = devm_add_action_or_reset(port->uport, unregister_region, cxlr); > + rc = devm_add_action_or_reset(port->uport_dev, unregister_region, cxlr); > if (rc) > return ERR_PTR(rc); > > - dev_dbg(port->uport, "%s: created %s\n", > + dev_dbg(port->uport_dev, "%s: created %s\n", > dev_name(&cxlrd->cxlsd.cxld.dev), dev_name(dev)); > return cxlr; > > @@ -2191,7 +2192,7 @@ static ssize_t delete_region_store(struct device *dev, > if (IS_ERR(cxlr)) > return PTR_ERR(cxlr); > > - devm_release_action(port->uport, unregister_region, cxlr); > + devm_release_action(port->uport_dev, unregister_region, cxlr); > put_device(&cxlr->dev); > > return len; > @@ -2356,7 +2357,8 @@ int cxl_get_poison_by_endpoint(struct cxl_port *port) > > rc = device_for_each_child(&port->dev, &ctx, poison_by_decoder); > if (rc == 1) > - rc = cxl_get_poison_unmapped(to_cxl_memdev(port->uport), &ctx); > + rc = cxl_get_poison_unmapped(to_cxl_memdev(port->uport_dev), > + &ctx); > > up_read(&cxl_region_rwsem); > return rc; > @@ -2732,7 +2734,7 @@ static struct cxl_region *construct_region(struct cxl_root_decoder *cxlrd, > > err: > up_write(&cxl_region_rwsem); > - devm_release_action(port->uport, unregister_region, cxlr); > + devm_release_action(port->uport_dev, unregister_region, cxlr); > return ERR_PTR(rc); > } > > diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h > index 7232c2a0e27c..754cfe59ae37 100644 > --- a/drivers/cxl/cxl.h > +++ b/drivers/cxl/cxl.h > @@ -536,7 +536,7 @@ struct cxl_dax_region { > * downstream port devices to construct a CXL memory > * decode hierarchy. > * @dev: this port's device > - * @uport: PCI or platform device implementing the upstream port capability > + * @uport_dev: PCI or platform device implementing the upstream port capability > * @host_bridge: Shortcut to the platform attach point for this port > * @id: id for port device-name > * @dports: cxl_dport instances referenced by decoders > @@ -555,7 +555,7 @@ struct cxl_dax_region { > */ > struct cxl_port { > struct device dev; > - struct device *uport; > + struct device *uport_dev; > struct device *host_bridge; > int id; > struct xarray dports; > @@ -641,21 +641,22 @@ struct cxl_region_ref { > /* > * The platform firmware device hosting the root is also the top of the > * CXL port topology. All other CXL ports have another CXL port as their > - * parent and their ->uport / host device is out-of-line of the port > + * parent and their ->uport_dev / host device is out-of-line of the port > * ancestry. > */ > static inline bool is_cxl_root(struct cxl_port *port) > { > - return port->uport == port->dev.parent; > + return port->uport_dev == port->dev.parent; > } > > bool is_cxl_port(const struct device *dev); > struct cxl_port *to_cxl_port(const struct device *dev); > struct pci_bus; > -int devm_cxl_register_pci_bus(struct device *host, struct device *uport, > +int devm_cxl_register_pci_bus(struct device *host, struct device *uport_dev, > struct pci_bus *bus); > struct pci_bus *cxl_port_to_pci_bus(struct cxl_port *port); > -struct cxl_port *devm_cxl_add_port(struct device *host, struct device *uport, > +struct cxl_port *devm_cxl_add_port(struct device *host, > + struct device *uport_dev, > resource_size_t component_reg_phys, > struct cxl_dport *parent_dport); > struct cxl_port *find_cxl_root(struct cxl_port *port); > diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h > index a2845a7a69d8..76743016b64c 100644 > --- a/drivers/cxl/cxlmem.h > +++ b/drivers/cxl/cxlmem.h > @@ -72,13 +72,13 @@ cxled_to_memdev(struct cxl_endpoint_decoder *cxled) > { > struct cxl_port *port = to_cxl_port(cxled->cxld.dev.parent); > > - return to_cxl_memdev(port->uport); > + return to_cxl_memdev(port->uport_dev); > } > > bool is_cxl_memdev(const struct device *dev); > static inline bool is_cxl_endpoint(struct cxl_port *port) > { > - return is_cxl_memdev(port->uport); > + return is_cxl_memdev(port->uport_dev); > } > > struct cxl_memdev *devm_cxl_add_memdev(struct cxl_dev_state *cxlds); > diff --git a/drivers/cxl/mem.c b/drivers/cxl/mem.c > index 45d4c32d78b0..4cc461c22b8b 100644 > --- a/drivers/cxl/mem.c > +++ b/drivers/cxl/mem.c > @@ -163,7 +163,7 @@ static int cxl_mem_probe(struct device *dev) > } > > if (dport->rch) > - endpoint_parent = parent_port->uport; > + endpoint_parent = parent_port->uport_dev; > else > endpoint_parent = &parent_port->dev; > > diff --git a/drivers/cxl/port.c b/drivers/cxl/port.c > index c23b6164e1c0..4cef2bf45ad2 100644 > --- a/drivers/cxl/port.c > +++ b/drivers/cxl/port.c > @@ -91,7 +91,7 @@ static int cxl_switch_port_probe(struct cxl_port *port) > static int cxl_endpoint_port_probe(struct cxl_port *port) > { > struct cxl_endpoint_dvsec_info info = { .port = port }; > - struct cxl_memdev *cxlmd = to_cxl_memdev(port->uport); > + struct cxl_memdev *cxlmd = to_cxl_memdev(port->uport_dev); > struct cxl_dev_state *cxlds = cxlmd->cxlds; > struct cxl_hdm *cxlhdm; > struct cxl_port *root; > diff --git a/tools/testing/cxl/test/cxl.c b/tools/testing/cxl/test/cxl.c > index f5c04787bcc8..4f62eb55f8b8 100644 > --- a/tools/testing/cxl/test/cxl.c > +++ b/tools/testing/cxl/test/cxl.c > @@ -754,7 +754,7 @@ static void mock_init_hdm_decoder(struct cxl_decoder *cxld) > /* check is endpoint is attach to host-bridge0 */ > port = cxled_to_port(cxled); > do { > - if (port->uport == &cxl_host_bridge[0]->dev) { > + if (port->uport_dev == &cxl_host_bridge[0]->dev) { > hb0 = true; > break; > } > @@ -889,7 +889,7 @@ static int mock_cxl_enumerate_decoders(struct cxl_hdm *cxlhdm, > mock_init_hdm_decoder(cxld); > > if (target_count) { > - rc = device_for_each_child(port->uport, &ctx, > + rc = device_for_each_child(port->uport_dev, &ctx, > map_targets); > if (rc) { > put_device(&cxld->dev); > @@ -919,29 +919,29 @@ static int mock_cxl_port_enumerate_dports(struct cxl_port *port) > int i, array_size; > > if (port->depth == 1) { > - if (is_multi_bridge(port->uport)) { > + if (is_multi_bridge(port->uport_dev)) { > array_size = ARRAY_SIZE(cxl_root_port); > array = cxl_root_port; > - } else if (is_single_bridge(port->uport)) { > + } else if (is_single_bridge(port->uport_dev)) { > array_size = ARRAY_SIZE(cxl_root_single); > array = cxl_root_single; > } else { > dev_dbg(&port->dev, "%s: unknown bridge type\n", > - dev_name(port->uport)); > + dev_name(port->uport_dev)); > return -ENXIO; > } > } else if (port->depth == 2) { > struct cxl_port *parent = to_cxl_port(port->dev.parent); > > - if (is_multi_bridge(parent->uport)) { > + if (is_multi_bridge(parent->uport_dev)) { > array_size = ARRAY_SIZE(cxl_switch_dport); > array = cxl_switch_dport; > - } else if (is_single_bridge(parent->uport)) { > + } else if (is_single_bridge(parent->uport_dev)) { > array_size = ARRAY_SIZE(cxl_swd_single); > array = cxl_swd_single; > } else { > dev_dbg(&port->dev, "%s: unknown bridge type\n", > - dev_name(port->uport)); > + dev_name(port->uport_dev)); > return -ENXIO; > } > } else { > @@ -954,9 +954,9 @@ static int mock_cxl_port_enumerate_dports(struct cxl_port *port) > struct platform_device *pdev = array[i]; > struct cxl_dport *dport; > > - if (pdev->dev.parent != port->uport) { > + if (pdev->dev.parent != port->uport_dev) { > dev_dbg(&port->dev, "%s: mismatch parent %s\n", > - dev_name(port->uport), > + dev_name(port->uport_dev), > dev_name(pdev->dev.parent)); > continue; > } > diff --git a/tools/testing/cxl/test/mock.c b/tools/testing/cxl/test/mock.c > index dbeef5c6f606..da554df50bac 100644 > --- a/tools/testing/cxl/test/mock.c > +++ b/tools/testing/cxl/test/mock.c > @@ -139,7 +139,7 @@ struct cxl_hdm *__wrap_devm_cxl_setup_hdm(struct cxl_port *port, > struct cxl_hdm *cxlhdm; > struct cxl_mock_ops *ops = get_cxl_mock_ops(&index); > > - if (ops && ops->is_mock_port(port->uport)) > + if (ops && ops->is_mock_port(port->uport_dev)) > cxlhdm = ops->devm_cxl_setup_hdm(port, info); > else > cxlhdm = devm_cxl_setup_hdm(port, info); > @@ -154,7 +154,7 @@ int __wrap_devm_cxl_enable_hdm(struct cxl_port *port, struct cxl_hdm *cxlhdm) > int index, rc; > struct cxl_mock_ops *ops = get_cxl_mock_ops(&index); > > - if (ops && ops->is_mock_port(port->uport)) > + if (ops && ops->is_mock_port(port->uport_dev)) > rc = 0; > else > rc = devm_cxl_enable_hdm(port, cxlhdm); > @@ -169,7 +169,7 @@ int __wrap_devm_cxl_add_passthrough_decoder(struct cxl_port *port) > int rc, index; > struct cxl_mock_ops *ops = get_cxl_mock_ops(&index); > > - if (ops && ops->is_mock_port(port->uport)) > + if (ops && ops->is_mock_port(port->uport_dev)) > rc = ops->devm_cxl_add_passthrough_decoder(port); > else > rc = devm_cxl_add_passthrough_decoder(port); > @@ -186,7 +186,7 @@ int __wrap_devm_cxl_enumerate_decoders(struct cxl_hdm *cxlhdm, > struct cxl_port *port = cxlhdm->port; > struct cxl_mock_ops *ops = get_cxl_mock_ops(&index); > > - if (ops && ops->is_mock_port(port->uport)) > + if (ops && ops->is_mock_port(port->uport_dev)) > rc = ops->devm_cxl_enumerate_decoders(cxlhdm, info); > else > rc = devm_cxl_enumerate_decoders(cxlhdm, info); > @@ -201,7 +201,7 @@ int __wrap_devm_cxl_port_enumerate_dports(struct cxl_port *port) > int rc, index; > struct cxl_mock_ops *ops = get_cxl_mock_ops(&index); > > - if (ops && ops->is_mock_port(port->uport)) > + if (ops && ops->is_mock_port(port->uport_dev)) > rc = ops->devm_cxl_port_enumerate_dports(port); > else > rc = devm_cxl_port_enumerate_dports(port);
diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c index 7c75e8832afb..82de858506c7 100644 --- a/drivers/cxl/core/port.c +++ b/drivers/cxl/core/port.c @@ -605,7 +605,7 @@ static int devm_cxl_link_parent_dport(struct device *host, if (!parent_dport) return 0; - rc = sysfs_create_link(&port->dev.kobj, &parent_dport->dport->kobj, + rc = sysfs_create_link(&port->dev.kobj, &parent_dport->dev->kobj, "parent_dport"); if (rc) return rc; @@ -658,7 +658,7 @@ static struct cxl_port *cxl_port_alloc(struct device *uport, if (iter->host_bridge) port->host_bridge = iter->host_bridge; else if (parent_dport->rch) - port->host_bridge = parent_dport->dport; + port->host_bridge = parent_dport->dev; else port->host_bridge = iter->uport; dev_dbg(uport, "host-bridge: %s\n", dev_name(port->host_bridge)); @@ -847,22 +847,22 @@ static struct cxl_dport *find_dport(struct cxl_port *port, int id) return NULL; } -static int add_dport(struct cxl_port *port, struct cxl_dport *new) +static int add_dport(struct cxl_port *port, struct cxl_dport *dport) { struct cxl_dport *dup; int rc; device_lock_assert(&port->dev); - dup = find_dport(port, new->port_id); + dup = find_dport(port, dport->port_id); if (dup) { dev_err(&port->dev, "unable to add dport%d-%s non-unique port id (%s)\n", - new->port_id, dev_name(new->dport), - dev_name(dup->dport)); + dport->port_id, dev_name(dport->dev), + dev_name(dup->dev)); return -EBUSY; } - rc = xa_insert(&port->dports, (unsigned long)new->dport, new, + rc = xa_insert(&port->dports, (unsigned long)dport->dev, dport, GFP_KERNEL); if (rc) return rc; @@ -895,8 +895,8 @@ static void cxl_dport_remove(void *data) struct cxl_dport *dport = data; struct cxl_port *port = dport->port; - xa_erase(&port->dports, (unsigned long) dport->dport); - put_device(dport->dport); + xa_erase(&port->dports, (unsigned long) dport->dev); + put_device(dport->dev); } static void cxl_dport_unlink(void *data) @@ -954,7 +954,7 @@ __devm_cxl_add_dport(struct cxl_port *port, struct device *dport_dev, dev_dbg(dport_dev, "Component Registers found for dport: %pa\n", &component_reg_phys); - dport->dport = dport_dev; + dport->dev = dport_dev; dport->port_id = port_id; dport->component_reg_phys = component_reg_phys; dport->port = port; diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c index f822de44bee0..8886c6201998 100644 --- a/drivers/cxl/core/region.c +++ b/drivers/cxl/core/region.c @@ -1162,7 +1162,7 @@ static int cxl_port_setup_targets(struct cxl_port *port, dev_dbg(&cxlr->dev, "%s:%s: %s expected %s at %d\n", dev_name(port->uport), dev_name(&port->dev), dev_name(&cxlsd->cxld.dev), - dev_name(ep->dport->dport), + dev_name(ep->dport->dev), cxl_rr->nr_targets_set); return -ENXIO; } @@ -1173,7 +1173,7 @@ static int cxl_port_setup_targets(struct cxl_port *port, cxl_rr->nr_targets_set += inc; dev_dbg(&cxlr->dev, "%s:%s target[%d] = %s for %s:%s @ %d\n", dev_name(port->uport), dev_name(&port->dev), - cxl_rr->nr_targets_set - 1, dev_name(ep->dport->dport), + cxl_rr->nr_targets_set - 1, dev_name(ep->dport->dev), dev_name(&cxlmd->dev), dev_name(&cxled->cxld.dev), pos); return 0; diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index 29e0bd2b8f2a..a8bda2c74a85 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -594,7 +594,7 @@ struct cxl_rcrb_info { /** * struct cxl_dport - CXL downstream port - * @dport: PCI bridge or firmware device representing the downstream link + * @dev: PCI bridge or firmware device representing the downstream link * @port: reference to cxl_port that contains this downstream port * @port_id: unique hardware identifier for dport in decoder target list * @component_reg_phys: downstream port component registers @@ -602,7 +602,7 @@ struct cxl_rcrb_info { * @rcrb: Data about the Root Complex Register Block layout */ struct cxl_dport { - struct device *dport; + struct device *dev; struct cxl_port *port; int port_id; resource_size_t component_reg_phys;