| Message ID | 20230602221604.155027-3-festevam@gmail.com (mailing list archive) |
|---|---|
| State | Awaiting Upstream, archived |
| Headers | show |
| Series | [1/3] ARM: dts: imx6sx: Remove LDB endpoint | expand |
Quoting Fabio Estevam (2023-06-02 15:16:04) > From: Fabio Estevam <festevam@denx.de> > > It is not a good idea to hardcode the LCDIF1 parent inside the > clock driver because some users may want to use a different clock > parent for LCDIF1. One of the reasons could be related to EMI tests. > > Remove the harcoded LCDIF1 parent as this is better described via > devicetree. > > Signed-off-by: Fabio Estevam <festevam@denx.de> > --- Do you need to check for the DT property and skip these clk_set_parent() calls if they're present? How does this work if the DT isn't updated at the same time?
Hi Stephen, On Thu, Jun 8, 2023 at 9:24 PM Stephen Boyd <sboyd@kernel.org> wrote: > Do you need to check for the DT property and skip these clk_set_parent() > calls if they're present? How does this work if the DT isn't updated at > the same time? Good point. I've just sent v2 with the DT property check as suggested. Thanks
diff --git a/drivers/clk/imx/clk-imx6sx.c b/drivers/clk/imx/clk-imx6sx.c index 3f1502933e59..b110258b9036 100644 --- a/drivers/clk/imx/clk-imx6sx.c +++ b/drivers/clk/imx/clk-imx6sx.c @@ -498,10 +498,6 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node) clk_set_parent(hws[IMX6SX_CLK_EIM_SLOW_SEL]->clk, hws[IMX6SX_CLK_PLL2_PFD2]->clk); clk_set_rate(hws[IMX6SX_CLK_EIM_SLOW]->clk, 132000000); - /* set parent clock for LCDIF1 pixel clock */ - clk_set_parent(hws[IMX6SX_CLK_LCDIF1_PRE_SEL]->clk, hws[IMX6SX_CLK_PLL5_VIDEO_DIV]->clk); - clk_set_parent(hws[IMX6SX_CLK_LCDIF1_SEL]->clk, hws[IMX6SX_CLK_LCDIF1_PODF]->clk); - /* Set the parent clks of PCIe lvds1 and pcie_axi to be pcie ref, axi */ if (clk_set_parent(hws[IMX6SX_CLK_LVDS1_SEL]->clk, hws[IMX6SX_CLK_PCIE_REF_125M]->clk)) pr_err("Failed to set pcie bus parent clk.\n");