| Message ID | 20230614193544.2114603-13-Frank.Li@nxp.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | dmaengine: edma: add freescale edma v3 support | expand |
On 14/06/2023 21:35, Frank Li wrote: > Extend Freescale eDMA driver bindings to support eDMA3 IP blocks in > i.MX8QM and i.MX8QXP SoCs. In i.MX93, both eDMA3 and eDMA4 are now. > > Signed-off-by: Frank Li <Frank.Li@nxp.com> > --- > .../devicetree/bindings/dma/fsl,edma.yaml | 99 +++++++++++++++++-- > 1 file changed, 92 insertions(+), 7 deletions(-) > > diff --git a/Documentation/devicetree/bindings/dma/fsl,edma.yaml b/Documentation/devicetree/bindings/dma/fsl,edma.yaml > index 5fd8fc604261..de8c44bd8a89 100644 > --- a/Documentation/devicetree/bindings/dma/fsl,edma.yaml > +++ b/Documentation/devicetree/bindings/dma/fsl,edma.yaml > @@ -21,32 +21,41 @@ properties: > - enum: > - fsl,vf610-edma > - fsl,imx7ulp-edma > + - fsl,imx8qm-adma > + - fsl,imx8qm-edma > + - fsl,imx93-edma3 > + - fsl,imx93-edma4 > - items: > - const: fsl,ls1028a-edma > - const: fsl,vf610-edma > > reg: > - minItems: 2 > + minItems: 1 > maxItems: 3 > > interrupts: > - minItems: 2 > - maxItems: 17 > + minItems: 1 > + maxItems: 64 > > interrupt-names: > - minItems: 2 > - maxItems: 17 > + minItems: 1 > + maxItems: 64 > > "#dma-cells": > - const: 2 > + enum: > + - 2 > + - 3 > > dma-channels: > - const: 32 > + minItems: 1 > + maxItems: 64 > > clocks: > + minItems: 1 > maxItems: 2 > > clock-names: > + minItems: 1 > maxItems: 2 > > big-endian: > @@ -65,6 +74,38 @@ required: > > allOf: > - $ref: dma-controller.yaml# > + - if: > + properties: > + compatible: > + contains: > + enum: > + - fsl,imx8qm-adma > + - fsl,imx8qm-edma > + - fsl,imx93-edma3 > + - fsl,imx93-edma4 > + then: > + properties: > + "#dma-cells": > + const: 3 > + # It is not necessary to write the interrupt name for each channel. > + # instead, you can simply maintain the sequential IRQ numbers as > + # defined for the DMA channels. > + interrupt-names: false > + clock-names: items: - const: dma clocks: maxItems: 1 You do not allow more than one clock, right? > + const: dma > + else: You already have two ifs, so you should not have else here, but rather make each if clause proper for your setup. BTW, the amount of differences point to very complicated schema, so you should think whether it makes sense to keep binding growing in the first place. > + properties: > + reg: > + minItems: 2 > + maxItems: 3 > + interrupts: > + minItems: 2 > + maxItems: 17 missing clocks restriction to minItems: 2 > + "#dma-cells": > + const: 2 > + dma-channels: > + const: 32 > + Best regards, Krzysztof
On Thu, Jun 15, 2023 at 12:52:18PM +0200, Krzysztof Kozlowski wrote: > On 14/06/2023 21:35, Frank Li wrote: > > + # It is not necessary to write the interrupt name for each channel. > > + # instead, you can simply maintain the sequential IRQ numbers as > > + # defined for the DMA channels. > > + interrupt-names: false > > + clock-names: > > items: > - const: dma > > clocks: > maxItems: 1 > > You do not allow more than one clock, right? Yes, at least now. Only 1 clock needed. > > > + const: dma > > + else: > > You already have two ifs, so you should not have else here, but rather > make each if clause proper for your setup. > > BTW, the amount of differences point to very complicated schema, so you > should think whether it makes sense to keep binding growing in the first > place. Any good ways if don't growing binding at the first place? > > > + properties: > > + reg: > > + minItems: 2 > > + maxItems: 3 > > + interrupts: > > + minItems: 2 > > + maxItems: 17 > > missing clocks restriction to minItems: 2 > > > > + "#dma-cells": > > + const: 2 > > + dma-channels: > > + const: 32 > > + > > > > Best regards, > Krzysztof >
diff --git a/Documentation/devicetree/bindings/dma/fsl,edma.yaml b/Documentation/devicetree/bindings/dma/fsl,edma.yaml index 5fd8fc604261..de8c44bd8a89 100644 --- a/Documentation/devicetree/bindings/dma/fsl,edma.yaml +++ b/Documentation/devicetree/bindings/dma/fsl,edma.yaml @@ -21,32 +21,41 @@ properties: - enum: - fsl,vf610-edma - fsl,imx7ulp-edma + - fsl,imx8qm-adma + - fsl,imx8qm-edma + - fsl,imx93-edma3 + - fsl,imx93-edma4 - items: - const: fsl,ls1028a-edma - const: fsl,vf610-edma reg: - minItems: 2 + minItems: 1 maxItems: 3 interrupts: - minItems: 2 - maxItems: 17 + minItems: 1 + maxItems: 64 interrupt-names: - minItems: 2 - maxItems: 17 + minItems: 1 + maxItems: 64 "#dma-cells": - const: 2 + enum: + - 2 + - 3 dma-channels: - const: 32 + minItems: 1 + maxItems: 64 clocks: + minItems: 1 maxItems: 2 clock-names: + minItems: 1 maxItems: 2 big-endian: @@ -65,6 +74,38 @@ required: allOf: - $ref: dma-controller.yaml# + - if: + properties: + compatible: + contains: + enum: + - fsl,imx8qm-adma + - fsl,imx8qm-edma + - fsl,imx93-edma3 + - fsl,imx93-edma4 + then: + properties: + "#dma-cells": + const: 3 + # It is not necessary to write the interrupt name for each channel. + # instead, you can simply maintain the sequential IRQ numbers as + # defined for the DMA channels. + interrupt-names: false + clock-names: + const: dma + else: + properties: + reg: + minItems: 2 + maxItems: 3 + interrupts: + minItems: 2 + maxItems: 17 + "#dma-cells": + const: 2 + dma-channels: + const: 32 + - if: properties: compatible: @@ -153,3 +194,47 @@ examples: clock-names = "dma", "dmamux0"; clocks = <&pcc2 IMX7ULP_CLK_DMA1>, <&pcc2 IMX7ULP_CLK_DMA_MUX1>; }; + + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/imx93-clock.h> + + dma-controller@44000000 { + compatible = "fsl,imx93-edma3"; + reg = <0x44000000 0x200000>; + #dma-cells = <3>; + dma-channels = <31>; + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_EDMA1_GATE>; + clock-names = "dma"; + };
Extend Freescale eDMA driver bindings to support eDMA3 IP blocks in i.MX8QM and i.MX8QXP SoCs. In i.MX93, both eDMA3 and eDMA4 are now. Signed-off-by: Frank Li <Frank.Li@nxp.com> --- .../devicetree/bindings/dma/fsl,edma.yaml | 99 +++++++++++++++++-- 1 file changed, 92 insertions(+), 7 deletions(-)