diff mbox series

[v2,5/6] hwmon: (k10temp) Define helper function to read CCD temp

Message ID 20230615160328.419610-6-yazen.ghannam@amd.com (mailing list archive)
State New, archived
Headers show
Series Enhance AMD SMN Error Checking | expand

Commit Message

Yazen Ghannam June 15, 2023, 4:03 p.m. UTC
The CCD temperature register is read in two places. These reads are done
using an AMD SMN access, and a number of parameters are needed for the
operation.

Move the SMN access and parameter gathering into a helper function in
order to simply the code flow. This also has a benefit of centralizing
the hardware register access in a single place in case fixes or special
decoding is required.

Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com>
---
Link:
https://lore.kernel.org/r/20230516202430.4157216-6-yazen.ghannam@amd.com

v1->v2:
* Address comments from Guenter.

 drivers/hwmon/k10temp.c | 14 +++++++++-----
 1 file changed, 9 insertions(+), 5 deletions(-)

Comments

Guenter Roeck June 16, 2023, 2:22 a.m. UTC | #1
On 6/15/23 09:03, Yazen Ghannam wrote:
> The CCD temperature register is read in two places. These reads are done
> using an AMD SMN access, and a number of parameters are needed for the
> operation.
> 
> Move the SMN access and parameter gathering into a helper function in
> order to simply the code flow. This also has a benefit of centralizing
> the hardware register access in a single place in case fixes or special
> decoding is required.
> 
> Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com>

Acked-by: Guenter Roeck <linux@roeck-us.net>

> ---
> Link:
> https://lore.kernel.org/r/20230516202430.4157216-6-yazen.ghannam@amd.com
> 
> v1->v2:
> * Address comments from Guenter.
> 
>   drivers/hwmon/k10temp.c | 14 +++++++++-----
>   1 file changed, 9 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/hwmon/k10temp.c b/drivers/hwmon/k10temp.c
> index 70f7b77e6ece..dfbba8b72f43 100644
> --- a/drivers/hwmon/k10temp.c
> +++ b/drivers/hwmon/k10temp.c
> @@ -150,6 +150,13 @@ static void read_tempreg_nb_zen(struct pci_dev *pdev, u32 *regval)
>   		*regval = 0;
>   }
>   
> +static int read_ccd_temp_reg(struct k10temp_data *data, int ccd, u32 *regval)
> +{
> +	u16 node_id = amd_pci_dev_to_node_id(data->pdev);
> +
> +	return amd_smn_read(node_id, ZEN_CCD_TEMP(data->ccd_offset, ccd), regval);
> +}
> +
>   static long get_raw_temp(struct k10temp_data *data)
>   {
>   	u32 regval;
> @@ -215,9 +222,7 @@ static int k10temp_read_temp(struct device *dev, u32 attr, int channel,
>   				*val = 0;
>   			break;
>   		case 2 ... 13:		/* Tccd{1-12} */
> -			ret = amd_smn_read(amd_pci_dev_to_node_id(data->pdev),
> -					   ZEN_CCD_TEMP(data->ccd_offset, channel - 2),
> -					   &regval);
> +			ret = read_ccd_temp_reg(data, channel - 2, &regval);
>   
>   			if (ret)
>   				return ret;
> @@ -389,8 +394,7 @@ static void k10temp_get_ccd_support(struct pci_dev *pdev,
>   		 * the register value. And this will incorrectly pass the TEMP_VALID
>   		 * bit check.
>   		 */
> -		if (amd_smn_read(amd_pci_dev_to_node_id(pdev),
> -				 ZEN_CCD_TEMP(data->ccd_offset, i), &regval))
> +		if (read_ccd_temp_reg(data, i, &regval))
>   			continue;
>   
>   		if (regval & ZEN_CCD_TEMP_VALID)
diff mbox series

Patch

diff --git a/drivers/hwmon/k10temp.c b/drivers/hwmon/k10temp.c
index 70f7b77e6ece..dfbba8b72f43 100644
--- a/drivers/hwmon/k10temp.c
+++ b/drivers/hwmon/k10temp.c
@@ -150,6 +150,13 @@  static void read_tempreg_nb_zen(struct pci_dev *pdev, u32 *regval)
 		*regval = 0;
 }
 
+static int read_ccd_temp_reg(struct k10temp_data *data, int ccd, u32 *regval)
+{
+	u16 node_id = amd_pci_dev_to_node_id(data->pdev);
+
+	return amd_smn_read(node_id, ZEN_CCD_TEMP(data->ccd_offset, ccd), regval);
+}
+
 static long get_raw_temp(struct k10temp_data *data)
 {
 	u32 regval;
@@ -215,9 +222,7 @@  static int k10temp_read_temp(struct device *dev, u32 attr, int channel,
 				*val = 0;
 			break;
 		case 2 ... 13:		/* Tccd{1-12} */
-			ret = amd_smn_read(amd_pci_dev_to_node_id(data->pdev),
-					   ZEN_CCD_TEMP(data->ccd_offset, channel - 2),
-					   &regval);
+			ret = read_ccd_temp_reg(data, channel - 2, &regval);
 
 			if (ret)
 				return ret;
@@ -389,8 +394,7 @@  static void k10temp_get_ccd_support(struct pci_dev *pdev,
 		 * the register value. And this will incorrectly pass the TEMP_VALID
 		 * bit check.
 		 */
-		if (amd_smn_read(amd_pci_dev_to_node_id(pdev),
-				 ZEN_CCD_TEMP(data->ccd_offset, i), &regval))
+		if (read_ccd_temp_reg(data, i, &regval))
 			continue;
 
 		if (regval & ZEN_CCD_TEMP_VALID)