| Message ID | 20230619090326.3039040-1-tejas.upadhyay@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915/mtl: Update workaround 14018778641 | expand |
Hi Tejas, On Mon, Jun 19, 2023 at 02:33:26PM +0530, Tejas Upadhyay wrote: > WA 14018778641 needs an update after recent > performance data on MTL, aligning driver here with > HW WA update. > > Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com> Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com> Andi
Hi Tejas, On Mon, Jun 19, 2023 at 02:33:26PM +0530, Tejas Upadhyay wrote: > WA 14018778641 needs an update after recent > performance data on MTL, aligning driver here with > HW WA update. > > Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com> pushed to drm-intel-gt-next. Thanks, Andi
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 4d2dece96011..5bef3fe0cd74 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -1710,7 +1710,6 @@ static void xelpg_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) { /* Wa_14018778641 / Wa_18018781329 */ - wa_mcr_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB); wa_mcr_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB); /* Wa_22016670082 */ @@ -1743,8 +1742,6 @@ xelpmp_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) * GT, the media GT's versions are regular singleton registers. */ wa_write_or(wal, XELPMP_GSC_MOD_CTRL, FORCE_MISS_FTLB); - wa_write_or(wal, XELPMP_VDBX_MOD_CTRL, FORCE_MISS_FTLB); - wa_write_or(wal, XELPMP_VEBX_MOD_CTRL, FORCE_MISS_FTLB); debug_dump_steering(gt); }
WA 14018778641 needs an update after recent performance data on MTL, aligning driver here with HW WA update. Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com> --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 3 --- 1 file changed, 3 deletions(-)