| Message ID | 20230614134716.1055862-1-a1ba.omarov@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | clk: rockchip: rk3568: Add PLL rate for 101MHz | expand |
bump
On Wed, Jun 14, 2023 at 04:47:16PM +0300, Alibek Omarov wrote: > This patch adds PLL setting for not so common resolution as 1920x720-50.00, > which can be set using 2500 horizontal signals and 808 vertical. > > Signed-off-by: Alibek Omarov <a1ba.omarov@gmail.com> Reviewed-by: Sascha Hauer <s.hauer@pengutronix.de> > --- > drivers/clk/rockchip/clk-rk3568.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/clk/rockchip/clk-rk3568.c b/drivers/clk/rockchip/clk-rk3568.c > index f85902e2590c..5dae960af4ce 100644 > --- a/drivers/clk/rockchip/clk-rk3568.c > +++ b/drivers/clk/rockchip/clk-rk3568.c > @@ -79,6 +79,7 @@ static struct rockchip_pll_rate_table rk3568_pll_rates[] = { > RK3036_PLL_RATE(135000000, 2, 45, 4, 1, 1, 0), > RK3036_PLL_RATE(119000000, 3, 119, 4, 2, 1, 0), > RK3036_PLL_RATE(108000000, 2, 45, 5, 1, 1, 0), > + RK3036_PLL_RATE(101000000, 1, 101, 6, 4, 1, 0), refdiv = 1 fbdiv = 101 postdiv1 = 6 postdiv2 = 4 ((24000000/1)*101)/6/4 = 101000000 Ok. Sascha
On Wed, 14 Jun 2023 16:47:16 +0300, Alibek Omarov wrote: > This patch adds PLL setting for not so common resolution as 1920x720-50.00, > which can be set using 2500 horizontal signals and 808 vertical. > > Applied, thanks! [1/1] clk: rockchip: rk3568: Add PLL rate for 101MHz commit: 294580c9b921946f0f6b964326ccbf2d1cd78f7a Best regards,
diff --git a/drivers/clk/rockchip/clk-rk3568.c b/drivers/clk/rockchip/clk-rk3568.c index f85902e2590c..5dae960af4ce 100644 --- a/drivers/clk/rockchip/clk-rk3568.c +++ b/drivers/clk/rockchip/clk-rk3568.c @@ -79,6 +79,7 @@ static struct rockchip_pll_rate_table rk3568_pll_rates[] = { RK3036_PLL_RATE(135000000, 2, 45, 4, 1, 1, 0), RK3036_PLL_RATE(119000000, 3, 119, 4, 2, 1, 0), RK3036_PLL_RATE(108000000, 2, 45, 5, 1, 1, 0), + RK3036_PLL_RATE(101000000, 1, 101, 6, 4, 1, 0), RK3036_PLL_RATE(100000000, 1, 150, 6, 6, 1, 0), RK3036_PLL_RATE(96000000, 1, 96, 6, 4, 1, 0), RK3036_PLL_RATE(78750000, 1, 96, 6, 4, 1, 0),
This patch adds PLL setting for not so common resolution as 1920x720-50.00, which can be set using 2500 horizontal signals and 808 vertical. Signed-off-by: Alibek Omarov <a1ba.omarov@gmail.com> --- drivers/clk/rockchip/clk-rk3568.c | 1 + 1 file changed, 1 insertion(+)