mbox series

[v4,0/8] i386: Make Intel PT configurable

Message ID 20230531084311.3807277-1-xiaoyao.li@intel.com (mailing list archive)
Headers show
Series i386: Make Intel PT configurable | expand

Message

Xiaoyao Li May 31, 2023, 8:43 a.m. UTC
Initial virtualization of Intel PT was added by making it as fixed
feature set of ICX's capabilities. However, it breaks the Intel PT exposure
on SPR machine because SPR has less PT capabilities of
CPUID(0x14,1):EBX[15:0].

This series aims to make Intel PT configurable that named CPU model can
define its own PT feature set and "-cpu host/max" can use host pass-through
feature set of Intel PT.

At the same time, it also ensures existing named CPU model to generate
the same PT CPUID set as before to not break live migration.

Changes in v4:
- rebase to 51bdb0b57a2d "Merge tag 'pull-tcg-20230530' of https://gitlab.com/rth7680/qemu into staging"
- cleanup Patch 6 by updating the commit message and remove unnecessary
  handlng;

v3: https://lore.kernel.org/qemu-devel/20221208062513.2589476-1-xiaoyao.li@intel.com/
- rebase to v7.2.0-rc4
- Add bit 7 and 8 of FEAT_14_0_EBX in Patch 3

v2: https://lore.kernel.org/qemu-devel/20220808085834.3227541-1-xiaoyao.li@intel.com/
Changes in v2:
- split out 3 patches (per Eduardo's comment)
- determine if the named cpu model uses default Intel PT capabilities (to
  be compatible with the old behavior) by condition that all PT feature
  leaves are all zero.

v1: https://lore.kernel.org/qemu-devel/20210909144150.1728418-1-xiaoyao.li@intel.com/


Xiaoyao Li (8):
  target/i386: Print CPUID subleaf info for unsupported feature
  target/i386/intel-pt: Fix INTEL_PT_ADDR_RANGES_NUM_MASK
  target/i386/intel-pt: Introduce FeatureWordInfo for Intel PT CPUID
    leaf 0x14
  target/i386/intel-pt: print special message for
    INTEL_PT_ADDR_RANGES_NUM
  target/i386/intel-pt: Rework/rename the default INTEL-PT feature set
  target/i386/intel-pt: Enable host pass through of Intel PT
  target/i386/intel-pt: Define specific PT feature set for
    IceLake-server, Snowridge and SapphireRapids
  target/i386/intel-pt: Access MSR_IA32_RTIT_ADDRn based on guest CPUID
    configuration

 target/i386/cpu.c     | 293 +++++++++++++++++++++++++++++++-----------
 target/i386/cpu.h     |  39 +++++-
 target/i386/kvm/kvm.c |   8 +-
 3 files changed, 261 insertions(+), 79 deletions(-)

Comments

Xiaoyao Li July 3, 2023, 2:03 a.m. UTC | #1
On 5/31/2023 4:43 PM, Xiaoyao Li wrote:
> Initial virtualization of Intel PT was added by making it as fixed
> feature set of ICX's capabilities. However, it breaks the Intel PT exposure
> on SPR machine because SPR has less PT capabilities of
> CPUID(0x14,1):EBX[15:0].
> 
> This series aims to make Intel PT configurable that named CPU model can
> define its own PT feature set and "-cpu host/max" can use host pass-through
> feature set of Intel PT.
> 
> At the same time, it also ensures existing named CPU model to generate
> the same PT CPUID set as before to not break live migration.

ping for comments.

QEMU maintainers,

It has been nearly two years since the first version. It's very 
appreciated if any of you can express any thought on it. E.g., the basic 
question, whether this is an useful fix? or just a vain work?

> Changes in v4:
> - rebase to 51bdb0b57a2d "Merge tag 'pull-tcg-20230530' of https://gitlab.com/rth7680/qemu into staging"
> - cleanup Patch 6 by updating the commit message and remove unnecessary
>    handlng;
> 
> v3: https://lore.kernel.org/qemu-devel/20221208062513.2589476-1-xiaoyao.li@intel.com/
> - rebase to v7.2.0-rc4
> - Add bit 7 and 8 of FEAT_14_0_EBX in Patch 3
> 
> v2: https://lore.kernel.org/qemu-devel/20220808085834.3227541-1-xiaoyao.li@intel.com/
> Changes in v2:
> - split out 3 patches (per Eduardo's comment)
> - determine if the named cpu model uses default Intel PT capabilities (to
>    be compatible with the old behavior) by condition that all PT feature
>    leaves are all zero.
> 
> v1: https://lore.kernel.org/qemu-devel/20210909144150.1728418-1-xiaoyao.li@intel.com/
> 
> 
> Xiaoyao Li (8):
>    target/i386: Print CPUID subleaf info for unsupported feature
>    target/i386/intel-pt: Fix INTEL_PT_ADDR_RANGES_NUM_MASK
>    target/i386/intel-pt: Introduce FeatureWordInfo for Intel PT CPUID
>      leaf 0x14
>    target/i386/intel-pt: print special message for
>      INTEL_PT_ADDR_RANGES_NUM
>    target/i386/intel-pt: Rework/rename the default INTEL-PT feature set
>    target/i386/intel-pt: Enable host pass through of Intel PT
>    target/i386/intel-pt: Define specific PT feature set for
>      IceLake-server, Snowridge and SapphireRapids
>    target/i386/intel-pt: Access MSR_IA32_RTIT_ADDRn based on guest CPUID
>      configuration
> 
>   target/i386/cpu.c     | 293 +++++++++++++++++++++++++++++++-----------
>   target/i386/cpu.h     |  39 +++++-
>   target/i386/kvm/kvm.c |   8 +-
>   3 files changed, 261 insertions(+), 79 deletions(-)
>