| Message ID | 20230622113341.657842-5-fabrizio.castro.jz@renesas.com (mailing list archive) |
|---|---|
| State | Mainlined |
| Commit | 9abaabde2fecccb2297228647796ecd82954c312 |
| Delegated to: | Geert Uytterhoeven |
| Headers | show |
| Series | spi: Add CSI support for Renesas RZ/V2M | expand |
On Thu, Jun 22, 2023 at 1:34 PM Fabrizio Castro <fabrizio.castro.jz@renesas.com> wrote: > The Renesas RZ/V2M comes with 6 Clocked Serial Interface (CSI) > IPs (CSI0, CSI1, CSI2, CSI3, CSI4, CSI5), but Linux is only > allowed access to CSI0 and CSI4. > > This commit adds SoC specific device tree support for CSI0 and > CSI4. > > Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com> > --- > > v2: no changes Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> i.e. will queue in renesas-devel for v6.6. Gr{oetje,eeting}s, Geert
diff --git a/arch/arm64/boot/dts/renesas/r9a09g011.dtsi b/arch/arm64/boot/dts/renesas/r9a09g011.dtsi index 46d67b200a66..33f2ecf42441 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g011.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g011.dtsi @@ -236,6 +236,34 @@ sys: system-controller@a3f03000 { reg = <0 0xa3f03000 0 0x400>; }; + csi0: spi@a4020000 { + compatible = "renesas,rzv2m-csi"; + reg = <0 0xa4020000 0 0x80>; + interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD R9A09G011_CSI0_CLK>, + <&cpg CPG_MOD R9A09G011_CPERI_GRPG_PCLK>; + clock-names = "csiclk", "pclk"; + resets = <&cpg R9A09G011_CSI_GPG_PRESETN>; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + csi4: spi@a4020200 { + compatible = "renesas,rzv2m-csi"; + reg = <0 0xa4020200 0 0x80>; + interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD R9A09G011_CSI4_CLK>, + <&cpg CPG_MOD R9A09G011_CPERI_GRPH_PCLK>; + clock-names = "csiclk", "pclk"; + resets = <&cpg R9A09G011_CSI_GPH_PRESETN>; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + i2c0: i2c@a4030000 { #address-cells = <1>; #size-cells = <0>;
The Renesas RZ/V2M comes with 6 Clocked Serial Interface (CSI) IPs (CSI0, CSI1, CSI2, CSI3, CSI4, CSI5), but Linux is only allowed access to CSI0 and CSI4. This commit adds SoC specific device tree support for CSI0 and CSI4. Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com> --- v2: no changes arch/arm64/boot/dts/renesas/r9a09g011.dtsi | 28 ++++++++++++++++++++++ 1 file changed, 28 insertions(+)