| Message ID | 20230627094327.134775-2-andi.shyti@linux.intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Update AUX invalidation sequence | expand |
On 6/27/2023 11:43 AM, Andi Shyti wrote: > Fix the 'NV' definition postfix that is supposed to be INV. > > Take the chance to also order properly the registers based on > their address and call the GEN12_GFX_CCS_AUX_INV address as > GEN12_CCS_AUX_INV like all the other similar registers. > > Remove also VD1, VD3 and VE1 registers that don't exist. > > Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com> Reviewed-by: Nirmoy Das <nirmoy.das@intel.com> > Cc: <stable@vger.kernel.org> # v5.8+ > --- > drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 8 ++++---- > drivers/gpu/drm/i915/gt/intel_gt_regs.h | 14 ++++++-------- > drivers/gpu/drm/i915/gt/intel_lrc.c | 6 +++--- > 3 files changed, 13 insertions(+), 15 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c > index 23857cc08eca1..563efee055602 100644 > --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c > +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c > @@ -287,8 +287,8 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode) > > if (!HAS_FLAT_CCS(rq->engine->i915)) { > /* hsdes: 1809175790 */ > - cs = gen12_emit_aux_table_inv(rq->engine->gt, > - cs, GEN12_GFX_CCS_AUX_NV); > + cs = gen12_emit_aux_table_inv(rq->engine->gt, cs, > + GEN12_CCS_AUX_INV); > } > > *cs++ = preparser_disable(false); > @@ -348,10 +348,10 @@ int gen12_emit_flush_xcs(struct i915_request *rq, u32 mode) > if (aux_inv) { /* hsdes: 1809175790 */ > if (rq->engine->class == VIDEO_DECODE_CLASS) > cs = gen12_emit_aux_table_inv(rq->engine->gt, > - cs, GEN12_VD0_AUX_NV); > + cs, GEN12_VD0_AUX_INV); > else > cs = gen12_emit_aux_table_inv(rq->engine->gt, > - cs, GEN12_VE0_AUX_NV); > + cs, GEN12_VE0_AUX_INV); > } > > if (mode & EMIT_INVALIDATE) > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > index 718cb2c80f79e..78b67a5336afc 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h > +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > @@ -332,9 +332,10 @@ > #define GEN8_PRIVATE_PAT_HI _MMIO(0x40e0 + 4) > #define GEN10_PAT_INDEX(index) _MMIO(0x40e0 + (index) * 4) > #define BSD_HWS_PGA_GEN7 _MMIO(0x4180) > -#define GEN12_GFX_CCS_AUX_NV _MMIO(0x4208) > -#define GEN12_VD0_AUX_NV _MMIO(0x4218) > -#define GEN12_VD1_AUX_NV _MMIO(0x4228) > + > +#define GEN12_CCS_AUX_INV _MMIO(0x4208) > +#define GEN12_VD0_AUX_INV _MMIO(0x4218) > +#define GEN12_VE0_AUX_INV _MMIO(0x4238) > > #define GEN8_RTCR _MMIO(0x4260) > #define GEN8_M1TCR _MMIO(0x4264) > @@ -342,14 +343,11 @@ > #define GEN8_BTCR _MMIO(0x426c) > #define GEN8_VTCR _MMIO(0x4270) > > -#define GEN12_VD2_AUX_NV _MMIO(0x4298) > -#define GEN12_VD3_AUX_NV _MMIO(0x42a8) > -#define GEN12_VE0_AUX_NV _MMIO(0x4238) > - > #define BLT_HWS_PGA_GEN7 _MMIO(0x4280) > > -#define GEN12_VE1_AUX_NV _MMIO(0x42b8) > +#define GEN12_VD2_AUX_INV _MMIO(0x4298) > #define AUX_INV REG_BIT(0) > + > #define VEBOX_HWS_PGA_GEN7 _MMIO(0x4380) > > #define GEN12_AUX_ERR_DBG _MMIO(0x43f4) > diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c > index a4ec20aaafe28..325f3dbfb90e6 100644 > --- a/drivers/gpu/drm/i915/gt/intel_lrc.c > +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c > @@ -1367,7 +1367,7 @@ gen12_emit_indirect_ctx_rcs(const struct intel_context *ce, u32 *cs) > /* hsdes: 1809175790 */ > if (!HAS_FLAT_CCS(ce->engine->i915)) > cs = gen12_emit_aux_table_inv(ce->engine->gt, > - cs, GEN12_GFX_CCS_AUX_NV); > + cs, GEN12_CCS_AUX_INV); > > /* Wa_16014892111 */ > if (IS_MTL_GRAPHICS_STEP(ce->engine->i915, M, STEP_A0, STEP_B0) || > @@ -1396,10 +1396,10 @@ gen12_emit_indirect_ctx_xcs(const struct intel_context *ce, u32 *cs) > if (!HAS_FLAT_CCS(ce->engine->i915)) { > if (ce->engine->class == VIDEO_DECODE_CLASS) > cs = gen12_emit_aux_table_inv(ce->engine->gt, > - cs, GEN12_VD0_AUX_NV); > + cs, GEN12_VD0_AUX_INV); > else if (ce->engine->class == VIDEO_ENHANCEMENT_CLASS) > cs = gen12_emit_aux_table_inv(ce->engine->gt, > - cs, GEN12_VE0_AUX_NV); > + cs, GEN12_VE0_AUX_INV); > } > > return cs;
diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c index 23857cc08eca1..563efee055602 100644 --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c @@ -287,8 +287,8 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode) if (!HAS_FLAT_CCS(rq->engine->i915)) { /* hsdes: 1809175790 */ - cs = gen12_emit_aux_table_inv(rq->engine->gt, - cs, GEN12_GFX_CCS_AUX_NV); + cs = gen12_emit_aux_table_inv(rq->engine->gt, cs, + GEN12_CCS_AUX_INV); } *cs++ = preparser_disable(false); @@ -348,10 +348,10 @@ int gen12_emit_flush_xcs(struct i915_request *rq, u32 mode) if (aux_inv) { /* hsdes: 1809175790 */ if (rq->engine->class == VIDEO_DECODE_CLASS) cs = gen12_emit_aux_table_inv(rq->engine->gt, - cs, GEN12_VD0_AUX_NV); + cs, GEN12_VD0_AUX_INV); else cs = gen12_emit_aux_table_inv(rq->engine->gt, - cs, GEN12_VE0_AUX_NV); + cs, GEN12_VE0_AUX_INV); } if (mode & EMIT_INVALIDATE) diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h index 718cb2c80f79e..78b67a5336afc 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h @@ -332,9 +332,10 @@ #define GEN8_PRIVATE_PAT_HI _MMIO(0x40e0 + 4) #define GEN10_PAT_INDEX(index) _MMIO(0x40e0 + (index) * 4) #define BSD_HWS_PGA_GEN7 _MMIO(0x4180) -#define GEN12_GFX_CCS_AUX_NV _MMIO(0x4208) -#define GEN12_VD0_AUX_NV _MMIO(0x4218) -#define GEN12_VD1_AUX_NV _MMIO(0x4228) + +#define GEN12_CCS_AUX_INV _MMIO(0x4208) +#define GEN12_VD0_AUX_INV _MMIO(0x4218) +#define GEN12_VE0_AUX_INV _MMIO(0x4238) #define GEN8_RTCR _MMIO(0x4260) #define GEN8_M1TCR _MMIO(0x4264) @@ -342,14 +343,11 @@ #define GEN8_BTCR _MMIO(0x426c) #define GEN8_VTCR _MMIO(0x4270) -#define GEN12_VD2_AUX_NV _MMIO(0x4298) -#define GEN12_VD3_AUX_NV _MMIO(0x42a8) -#define GEN12_VE0_AUX_NV _MMIO(0x4238) - #define BLT_HWS_PGA_GEN7 _MMIO(0x4280) -#define GEN12_VE1_AUX_NV _MMIO(0x42b8) +#define GEN12_VD2_AUX_INV _MMIO(0x4298) #define AUX_INV REG_BIT(0) + #define VEBOX_HWS_PGA_GEN7 _MMIO(0x4380) #define GEN12_AUX_ERR_DBG _MMIO(0x43f4) diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index a4ec20aaafe28..325f3dbfb90e6 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -1367,7 +1367,7 @@ gen12_emit_indirect_ctx_rcs(const struct intel_context *ce, u32 *cs) /* hsdes: 1809175790 */ if (!HAS_FLAT_CCS(ce->engine->i915)) cs = gen12_emit_aux_table_inv(ce->engine->gt, - cs, GEN12_GFX_CCS_AUX_NV); + cs, GEN12_CCS_AUX_INV); /* Wa_16014892111 */ if (IS_MTL_GRAPHICS_STEP(ce->engine->i915, M, STEP_A0, STEP_B0) || @@ -1396,10 +1396,10 @@ gen12_emit_indirect_ctx_xcs(const struct intel_context *ce, u32 *cs) if (!HAS_FLAT_CCS(ce->engine->i915)) { if (ce->engine->class == VIDEO_DECODE_CLASS) cs = gen12_emit_aux_table_inv(ce->engine->gt, - cs, GEN12_VD0_AUX_NV); + cs, GEN12_VD0_AUX_INV); else if (ce->engine->class == VIDEO_ENHANCEMENT_CLASS) cs = gen12_emit_aux_table_inv(ce->engine->gt, - cs, GEN12_VE0_AUX_NV); + cs, GEN12_VE0_AUX_INV); } return cs;
Fix the 'NV' definition postfix that is supposed to be INV. Take the chance to also order properly the registers based on their address and call the GEN12_GFX_CCS_AUX_INV address as GEN12_CCS_AUX_INV like all the other similar registers. Remove also VD1, VD3 and VE1 registers that don't exist. Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com> Cc: <stable@vger.kernel.org> # v5.8+ --- drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 8 ++++---- drivers/gpu/drm/i915/gt/intel_gt_regs.h | 14 ++++++-------- drivers/gpu/drm/i915/gt/intel_lrc.c | 6 +++--- 3 files changed, 13 insertions(+), 15 deletions(-)