| Message ID | 77fe66271044a18871e1dfb80bbb481617197d18.1689065318.git.quic_varada@quicinc.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Enable IPQ5332 USB2 | expand |
On 11/07/2023 10:51, Varadarajan Narayanan wrote: > Document the M31 USB2 phy present in IPQ5332. > > Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com> > Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> > --- > v3: > Incorporate review comments. Will bring in ipq5018 compatible > string while posting ipq5018 usb patchset. > > v1: > Rename qcom,m31.yaml -> qcom,ipq5332-usb-hsphy.yaml > Drop default binding "m31,usb-hsphy" > Add clock > Remove 'oneOf' from compatible > Remove 'qscratch' region from register space as it is not needed > Remove reset-names > Fix the example definition > --- > .../bindings/phy/qcom,ipq5332-usb-hsphy.yaml | 49 ++++++++++++++++++++++ > 1 file changed, 49 insertions(+) > create mode 100644 Documentation/devicetree/bindings/phy/qcom,ipq5332-usb-hsphy.yaml > > diff --git a/Documentation/devicetree/bindings/phy/qcom,ipq5332-usb-hsphy.yaml b/Documentation/devicetree/bindings/phy/qcom,ipq5332-usb-hsphy.yaml > new file mode 100644 > index 0000000..2cfdd73 > --- /dev/null > +++ b/Documentation/devicetree/bindings/phy/qcom,ipq5332-usb-hsphy.yaml > @@ -0,0 +1,49 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/phy/qcom,ipq5332-usb-hsphy.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: M31 (https://www.m31tech.com) USB PHY The URL should rather go to description, not the title. Title is like document title. > + > +maintainers: > + - Sricharan Ramabadhran <quic_srichara@quicinc.com> > + - Varadarajan Narayanan <quic_varada@quicinc.org> > + > +description: > + USB M31 PHY found in Qualcomm IPQ5018, IPQ5332 SoCs. > + > +properties: > + compatible: > + enum: > + - qcom,ipq5332-usb-hsphy > + > + reg: > + maxItems: 1 > + > + clocks: > + maxItems: 1 > + > + clock-names: > + maxItems: 1 Drop > + contains: Drop > + items: > + - const: cfg_ahb > + > + resets: > + maxItems: 1 > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/clock/qcom,ipq5332-gcc.h> > + usbphy0: ipq5332-hsphy@7b000 { Node names should be generic. See also an explanation and list of examples (not exhaustive) in DT specification: https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation Best regards, Krzysztof
On 11/07/2023 10:51, Varadarajan Narayanan wrote: > Document the M31 USB2 phy present in IPQ5332. > > Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com> > Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> > --- > v3: > Incorporate review comments. Will bring in ipq5018 compatible > string while posting ipq5018 usb patchset. > > v1: > Rename qcom,m31.yaml -> qcom,ipq5332-usb-hsphy.yaml > Drop default binding "m31,usb-hsphy" > Add clock > Remove 'oneOf' from compatible > Remove 'qscratch' region from register space as it is not needed > Remove reset-names > Fix the example definition > --- > .../bindings/phy/qcom,ipq5332-usb-hsphy.yaml | 49 ++++++++++++++++++++++ > 1 file changed, 49 insertions(+) > create mode 100644 Documentation/devicetree/bindings/phy/qcom,ipq5332-usb-hsphy.yaml > > diff --git a/Documentation/devicetree/bindings/phy/qcom,ipq5332-usb-hsphy.yaml b/Documentation/devicetree/bindings/phy/qcom,ipq5332-usb-hsphy.yaml > new file mode 100644 > index 0000000..2cfdd73 > --- /dev/null > +++ b/Documentation/devicetree/bindings/phy/qcom,ipq5332-usb-hsphy.yaml > @@ -0,0 +1,49 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/phy/qcom,ipq5332-usb-hsphy.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: M31 (https://www.m31tech.com) USB PHY > + > +maintainers: > + - Sricharan Ramabadhran <quic_srichara@quicinc.com> > + - Varadarajan Narayanan <quic_varada@quicinc.org> I was wondering why I keep receiving delays/bounces for my emails in this thread... and here we have. Please correct your email. Best regards, Krzysztof
diff --git a/Documentation/devicetree/bindings/phy/qcom,ipq5332-usb-hsphy.yaml b/Documentation/devicetree/bindings/phy/qcom,ipq5332-usb-hsphy.yaml new file mode 100644 index 0000000..2cfdd73 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/qcom,ipq5332-usb-hsphy.yaml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/qcom,ipq5332-usb-hsphy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: M31 (https://www.m31tech.com) USB PHY + +maintainers: + - Sricharan Ramabadhran <quic_srichara@quicinc.com> + - Varadarajan Narayanan <quic_varada@quicinc.org> + +description: + USB M31 PHY found in Qualcomm IPQ5018, IPQ5332 SoCs. + +properties: + compatible: + enum: + - qcom,ipq5332-usb-hsphy + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + maxItems: 1 + contains: + items: + - const: cfg_ahb + + resets: + maxItems: 1 + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,ipq5332-gcc.h> + usbphy0: ipq5332-hsphy@7b000 { + compatible = "qcom,ipq5332-usb-hsphy"; + reg = <0x0007b000 0x12c>; + + clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>; + clock-names = "cfg_ahb"; + + resets = <&gcc GCC_QUSB2_0_PHY_BCR>; + };