diff mbox series

arm64: dts: imx8mm-venice-gw7904: enable UART1 hardware flow control

Message ID 20230606153819.1449257-1-tharvey@gateworks.com (mailing list archive)
State New, archived
Headers show
Series arm64: dts: imx8mm-venice-gw7904: enable UART1 hardware flow control | expand

Commit Message

Tim Harvey June 6, 2023, 3:38 p.m. UTC 
On the GW7904 uart1 can use UART3_TX/RX for hardware flow control
which was the desired default configuration. Remove uart3 and configure
uart1 for hardware flow control.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
---
 .../dts/freescale/imx8mm-venice-gw7904.dts     | 18 ++++--------------
 1 file changed, 4 insertions(+), 14 deletions(-)

Comments

Shawn Guo July 17, 2023, 12:15 a.m. UTC | #1 
On Tue, Jun 06, 2023 at 08:38:19AM -0700, Tim Harvey wrote:
> On the GW7904 uart1 can use UART3_TX/RX for hardware flow control
> which was the desired default configuration. Remove uart3 and configure
> uart1 for hardware flow control.
> 
> Signed-off-by: Tim Harvey <tharvey@gateworks.com>

Applied, thanks!
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dts
index 93088fa1c3b9..c12e3f4f800f 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dts
@@ -636,6 +636,8 @@  &pgc_mipi {
 &uart1 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_uart1>;
+	cts-gpios = <&gpio5 26 GPIO_ACTIVE_LOW>;
+	rts-gpios = <&gpio5 27 GPIO_ACTIVE_LOW>;
 	status = "okay";
 };
 
@@ -646,13 +648,6 @@  &uart2 {
 	status = "okay";
 };
 
-/* off-board RS232 */
-&uart3 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_uart3>;
-	status = "okay";
-};
-
 &usbotg1 {
 	dr_mode = "host";
 	disable-over-current;
@@ -814,6 +809,8 @@  pinctrl_uart1: uart1grp {
 		fsl,pins = <
 			MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX	0x140
 			MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX	0x140
+			MX8MM_IOMUXC_UART3_RXD_GPIO5_IO26	0x140 /* CTS# in */
+			MX8MM_IOMUXC_UART3_TXD_GPIO5_IO27	0x140 /* RTS# out */
 		>;
 	};
 
@@ -824,13 +821,6 @@  MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX	0x140
 		>;
 	};
 
-	pinctrl_uart3: uart3grp {
-		fsl,pins = <
-			MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX	0x140
-			MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX	0x140
-		>;
-	};
-
 	pinctrl_usdhc2: usdhc2grp {
 		fsl,pins = <
 			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x190