| Message ID | 20230710094328.1359377-3-s-vadapalli@ti.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add MAIN CPSW2G DT support for J721S2 | expand |
On 7/10/23 3:13 PM, Siddharth Vadapalli wrote: > From: Kishon Vijay Abraham I <kishon@ti.com> > > The MAIN CPSW2G instance of CPSW on J721S2 SoC can be enabled with the GESI > Expansion Board connected to the J7 Common-Proc-Board. Use the overlay > to enable this. > > Add alias for the MAIN CPSW2G port to enable kernel to fetch MAC address > directly from U-Boot. > > Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> > Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> > --- > arch/arm64/boot/dts/ti/Makefile | 2 + > .../dts/ti/k3-j721s2-evm-gesi-exp-board.dtso | 85 +++++++++++++++++++ > 2 files changed, 87 insertions(+) > create mode 100644 arch/arm64/boot/dts/ti/k3-j721s2-evm-gesi-exp-board.dtso > > diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile > index 6dd7b6f1d6ab..019a8be19b93 100644 > --- a/arch/arm64/boot/dts/ti/Makefile > +++ b/arch/arm64/boot/dts/ti/Makefile > @@ -51,6 +51,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-j721e-sk.dtb > # Boards with J721s2 SoC > dtb-$(CONFIG_ARCH_K3) += k3-am68-sk-base-board.dtb > dtb-$(CONFIG_ARCH_K3) += k3-j721s2-common-proc-board.dtb > +dtb-$(CONFIG_ARCH_K3) += k3-j721s2-evm-gesi-exp-board.dtbo > > # Boards with J784s4 SoC > dtb-$(CONFIG_ARCH_K3) += k3-am69-sk.dtb > @@ -58,3 +59,4 @@ dtb-$(CONFIG_ARCH_K3) += k3-j784s4-evm.dtb > > # Enable support for device-tree overlays > DTC_FLAGS_k3-am6548-iot2050-advanced-m2 += -@ > +DTC_FLAGS_k3-j721s2-common-proc-board += -@ > diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-evm-gesi-exp-board.dtso b/arch/arm64/boot/dts/ti/k3-j721s2-evm-gesi-exp-board.dtso > new file mode 100644 > index 000000000000..9ababfeef904 > --- /dev/null > +++ b/arch/arm64/boot/dts/ti/k3-j721s2-evm-gesi-exp-board.dtso > @@ -0,0 +1,85 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/** > + * DT Overlay for MAIN CPSW2G using GESI Expansion Board with J7 common processor board. > + * > + * GESI Board Product Link: https://www.ti.com/tool/J7EXPCXEVM > + * > + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ > + */ > + > +/dts-v1/; > +/plugin/; > + > +#include <dt-bindings/gpio/gpio.h> > +#include <dt-bindings/net/ti-dp83867.h> > + > +#include "k3-pinctrl.h" > + > +&{/} { > + aliases { > + ethernet1 = "/bus@100000/ethernet@c200000/ethernet-ports/port@1"; > + }; > +}; > + > +&main_pmx0 { > + main_cpsw_mdio_pins_default: main-cpsw-mdio-pins-default { > + pinctrl-single,pins = < > + J721S2_IOPAD(0x0c0, PIN_OUTPUT, 6) /* (T28) MCASP1_AXR0.MDIO0_MDC */ > + J721S2_IOPAD(0x0bc, PIN_INPUT, 6) /* (V28) MCASP1_AFSX.MDIO0_MDIO */ > + >; > + }; > + > + rgmii1_pins_default: rgmii1-pins-default { > + pinctrl-single,pins = < > + J721S2_IOPAD(0x0b8, PIN_INPUT, 6) /* (AA24) MCASP1_ACLKX.RGMII1_RD0 */ > + J721S2_IOPAD(0x0a0, PIN_INPUT, 6) /* (AB25) MCASP0_AXR12.RGMII1_RD1 */ > + J721S2_IOPAD(0x0a4, PIN_INPUT, 6) /* (T23) MCASP0_AXR13.RGMII1_RD2 */ > + J721S2_IOPAD(0x0a8, PIN_INPUT, 6) /* (U24) MCASP0_AXR14.RGMII1_RD3 */ > + J721S2_IOPAD(0x0b0, PIN_INPUT, 6) /* (AD26) MCASP1_AXR3.RGMII1_RXC */ > + J721S2_IOPAD(0x0ac, PIN_INPUT, 6) /* (AC25) MCASP0_AXR15.RGMII1_RX_CTL */ > + J721S2_IOPAD(0x08c, PIN_OUTPUT, 6) /* (T25) MCASP0_AXR7.RGMII1_TD0 */ > + J721S2_IOPAD(0x090, PIN_OUTPUT, 6) /* (W24) MCASP0_AXR8.RGMII1_TD1 */ > + J721S2_IOPAD(0x094, PIN_OUTPUT, 6) /* (AA25) MCASP0_AXR9.RGMII1_TD2 */ > + J721S2_IOPAD(0x098, PIN_OUTPUT, 6) /* (V25) MCASP0_AXR10.RGMII1_TD3 */ > + J721S2_IOPAD(0x0b4, PIN_OUTPUT, 6) /* (U25) MCASP1_AXR4.RGMII1_TXC */ > + J721S2_IOPAD(0x09c, PIN_OUTPUT, 6) /* (T24) MCASP0_AXR11.RGMII1_TX_CTL */ > + >; > + }; > +}; > + > +&exp1 { > + p15 { > + /* P15 - EXP_MUX2 */ > + gpio-hog; > + gpios = <13 GPIO_ACTIVE_HIGH>; > + output-high; > + line-name = "EXP_MUX2"; > + }; > +}; > + > +&main_cpsw { > + status = "okay"; > + pinctrl-names = "default"; > + pinctrl-0 = <&rgmii1_pins_default>; > +}; > + > +&main_cpsw_mdio { > + status = "okay"; > + pinctrl-names = "default"; > + pinctrl-0 = <&main_cpsw_mdio_pins_default>; > + #address-cells = <1>; > + #size-cells = <0>; > + > + main_cpsw_phy0: ethernet-phy@0 { > + reg = <0>; > + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; > + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; > + ti,min-output-impedance; > + }; > +}; > + > +&main_cpsw_port1 { > + status = "okay"; > + phy-mode = "rgmii-rxid"; > + phy-handle = <&main_cpsw_phy0>; > +}; Reviewed-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
On 19/07/2023 11:45, Ravi Gunasekaran wrote: > > > On 7/10/23 3:13 PM, Siddharth Vadapalli wrote: >> From: Kishon Vijay Abraham I <kishon@ti.com> >> >> The MAIN CPSW2G instance of CPSW on J721S2 SoC can be enabled with the GESI >> Expansion Board connected to the J7 Common-Proc-Board. Use the overlay >> to enable this. >> Trim your replies. Best regards, Krzysztof
diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index 6dd7b6f1d6ab..019a8be19b93 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -51,6 +51,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-j721e-sk.dtb # Boards with J721s2 SoC dtb-$(CONFIG_ARCH_K3) += k3-am68-sk-base-board.dtb dtb-$(CONFIG_ARCH_K3) += k3-j721s2-common-proc-board.dtb +dtb-$(CONFIG_ARCH_K3) += k3-j721s2-evm-gesi-exp-board.dtbo # Boards with J784s4 SoC dtb-$(CONFIG_ARCH_K3) += k3-am69-sk.dtb @@ -58,3 +59,4 @@ dtb-$(CONFIG_ARCH_K3) += k3-j784s4-evm.dtb # Enable support for device-tree overlays DTC_FLAGS_k3-am6548-iot2050-advanced-m2 += -@ +DTC_FLAGS_k3-j721s2-common-proc-board += -@ diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-evm-gesi-exp-board.dtso b/arch/arm64/boot/dts/ti/k3-j721s2-evm-gesi-exp-board.dtso new file mode 100644 index 000000000000..9ababfeef904 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j721s2-evm-gesi-exp-board.dtso @@ -0,0 +1,85 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * DT Overlay for MAIN CPSW2G using GESI Expansion Board with J7 common processor board. + * + * GESI Board Product Link: https://www.ti.com/tool/J7EXPCXEVM + * + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/net/ti-dp83867.h> + +#include "k3-pinctrl.h" + +&{/} { + aliases { + ethernet1 = "/bus@100000/ethernet@c200000/ethernet-ports/port@1"; + }; +}; + +&main_pmx0 { + main_cpsw_mdio_pins_default: main-cpsw-mdio-pins-default { + pinctrl-single,pins = < + J721S2_IOPAD(0x0c0, PIN_OUTPUT, 6) /* (T28) MCASP1_AXR0.MDIO0_MDC */ + J721S2_IOPAD(0x0bc, PIN_INPUT, 6) /* (V28) MCASP1_AFSX.MDIO0_MDIO */ + >; + }; + + rgmii1_pins_default: rgmii1-pins-default { + pinctrl-single,pins = < + J721S2_IOPAD(0x0b8, PIN_INPUT, 6) /* (AA24) MCASP1_ACLKX.RGMII1_RD0 */ + J721S2_IOPAD(0x0a0, PIN_INPUT, 6) /* (AB25) MCASP0_AXR12.RGMII1_RD1 */ + J721S2_IOPAD(0x0a4, PIN_INPUT, 6) /* (T23) MCASP0_AXR13.RGMII1_RD2 */ + J721S2_IOPAD(0x0a8, PIN_INPUT, 6) /* (U24) MCASP0_AXR14.RGMII1_RD3 */ + J721S2_IOPAD(0x0b0, PIN_INPUT, 6) /* (AD26) MCASP1_AXR3.RGMII1_RXC */ + J721S2_IOPAD(0x0ac, PIN_INPUT, 6) /* (AC25) MCASP0_AXR15.RGMII1_RX_CTL */ + J721S2_IOPAD(0x08c, PIN_OUTPUT, 6) /* (T25) MCASP0_AXR7.RGMII1_TD0 */ + J721S2_IOPAD(0x090, PIN_OUTPUT, 6) /* (W24) MCASP0_AXR8.RGMII1_TD1 */ + J721S2_IOPAD(0x094, PIN_OUTPUT, 6) /* (AA25) MCASP0_AXR9.RGMII1_TD2 */ + J721S2_IOPAD(0x098, PIN_OUTPUT, 6) /* (V25) MCASP0_AXR10.RGMII1_TD3 */ + J721S2_IOPAD(0x0b4, PIN_OUTPUT, 6) /* (U25) MCASP1_AXR4.RGMII1_TXC */ + J721S2_IOPAD(0x09c, PIN_OUTPUT, 6) /* (T24) MCASP0_AXR11.RGMII1_TX_CTL */ + >; + }; +}; + +&exp1 { + p15 { + /* P15 - EXP_MUX2 */ + gpio-hog; + gpios = <13 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "EXP_MUX2"; + }; +}; + +&main_cpsw { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii1_pins_default>; +}; + +&main_cpsw_mdio { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_cpsw_mdio_pins_default>; + #address-cells = <1>; + #size-cells = <0>; + + main_cpsw_phy0: ethernet-phy@0 { + reg = <0>; + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; + ti,min-output-impedance; + }; +}; + +&main_cpsw_port1 { + status = "okay"; + phy-mode = "rgmii-rxid"; + phy-handle = <&main_cpsw_phy0>; +};