| Message ID | 373259d4ac9ac0b9e1e64ad96d60a9bbd35b85aa.1690439335.git.chenfeiyang@loongson.cn (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Netdev Maintainers |
| Headers | show |
| Series | stmmac: Add Loongson platform support | expand |
| Context | Check | Description |
|---|---|---|
| netdev/tree_selection | success | Guessing tree name failed - patch did not apply |
On Thu, Jul 27, 2023 at 03:15:46PM +0800, Feiyang Chen wrote: > Some platforms have dwmac1000 implementations that support multi- > channel. Extend the functions to add multi-channel support. > > + priv->plat->dwmac_is_loongson = false; I don't know this driver, so my comments could be wrong... Is this specific to loongson, or multi-channel? If you look at the other bool in plat, they are all for features, not machines? Could this actually be called priv->multi_chan_en ? Andrew
Hi Feiyang, kernel test robot noticed the following build warnings: [auto build test WARNING on net/main] [also build test WARNING on linus/master v6.5-rc3] [cannot apply to sunxi/sunxi/for-next net-next/main horms-ipvs/master next-20230727] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch#_base_tree_information] url: https://github.com/intel-lab-lkp/linux/commits/Feiyang-Chen/net-stmmac-Pass-stmmac_priv-and-chan-in-some-callbacks/20230727-155954 base: net/main patch link: https://lore.kernel.org/r/373259d4ac9ac0b9e1e64ad96d60a9bbd35b85aa.1690439335.git.chenfeiyang%40loongson.cn patch subject: [PATCH v2 03/10] net: stmmac: dwmac1000: Add multi-channel support config: alpha-randconfig-r012-20230727 (https://download.01.org/0day-ci/archive/20230727/202307271817.7iWaIMw7-lkp@intel.com/config) compiler: alpha-linux-gcc (GCC) 12.3.0 reproduce: (https://download.01.org/0day-ci/archive/20230727/202307271817.7iWaIMw7-lkp@intel.com/reproduce) If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot <lkp@intel.com> | Closes: https://lore.kernel.org/oe-kbuild-all/202307271817.7iWaIMw7-lkp@intel.com/ All warnings (new ones prefixed by >>): >> drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c:114:6: warning: no previous prototype for 'dwmac1000_dma_init_channel' [-Wmissing-prototypes] 114 | void dwmac1000_dma_init_channel(struct stmmac_priv *priv, void __iomem *ioaddr, | ^~~~~~~~~~~~~~~~~~~~~~~~~~ vim +/dwmac1000_dma_init_channel +114 drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c 113 > 114 void dwmac1000_dma_init_channel(struct stmmac_priv *priv, void __iomem *ioaddr, 115 struct stmmac_dma_cfg *dma_cfg, 116 u32 chan) 117 { 118 u32 value; 119 int txpbl = dma_cfg->txpbl ?: dma_cfg->pbl; 120 int rxpbl = dma_cfg->rxpbl ?: dma_cfg->pbl; 121 122 if (!priv->plat->dwmac_is_loongson) 123 return; 124 125 /* common channel control register config */ 126 value = readl(ioaddr + DMA_BUS_MODE + chan * DMA_CHAN_OFFSET); 127 128 /* 129 * Set the DMA PBL (Programmable Burst Length) mode. 130 * 131 * Note: before stmmac core 3.50 this mode bit was 4xPBL, and 132 * post 3.5 mode bit acts as 8*PBL. 133 */ 134 if (dma_cfg->pblx8) 135 value |= DMA_BUS_MODE_MAXPBL; 136 value |= DMA_BUS_MODE_USP; 137 value &= ~(DMA_BUS_MODE_PBL_MASK | DMA_BUS_MODE_RPBL_MASK); 138 value |= (txpbl << DMA_BUS_MODE_PBL_SHIFT); 139 value |= (rxpbl << DMA_BUS_MODE_RPBL_SHIFT); 140 141 /* Set the Fixed burst mode */ 142 if (dma_cfg->fixed_burst) 143 value |= DMA_BUS_MODE_FB; 144 145 /* Mixed Burst has no effect when fb is set */ 146 if (dma_cfg->mixed_burst) 147 value |= DMA_BUS_MODE_MB; 148 149 value |= DMA_BUS_MODE_ATDS; 150 151 if (dma_cfg->aal) 152 value |= DMA_BUS_MODE_AAL; 153 154 writel(value, ioaddr + DMA_BUS_MODE + chan * DMA_CHAN_OFFSET); 155 156 /* Mask interrupts by writing to CSR7 */ 157 writel(DMA_INTR_DEFAULT_MASK, 158 ioaddr + DMA_INTR_ENA + chan * DMA_CHAN_OFFSET); 159 } 160
Hi Feiyang, kernel test robot noticed the following build warnings: [auto build test WARNING on net/main] [also build test WARNING on linus/master v6.5-rc3] [cannot apply to sunxi/sunxi/for-next net-next/main horms-ipvs/master next-20230727] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch#_base_tree_information] url: https://github.com/intel-lab-lkp/linux/commits/Feiyang-Chen/net-stmmac-Pass-stmmac_priv-and-chan-in-some-callbacks/20230727-155954 base: net/main patch link: https://lore.kernel.org/r/373259d4ac9ac0b9e1e64ad96d60a9bbd35b85aa.1690439335.git.chenfeiyang%40loongson.cn patch subject: [PATCH v2 03/10] net: stmmac: dwmac1000: Add multi-channel support config: i386-buildonly-randconfig-r006-20230727 (https://download.01.org/0day-ci/archive/20230728/202307280004.UhGTxBbU-lkp@intel.com/config) compiler: clang version 16.0.4 (https://github.com/llvm/llvm-project.git ae42196bc493ffe877a7e3dff8be32035dea4d07) reproduce: (https://download.01.org/0day-ci/archive/20230728/202307280004.UhGTxBbU-lkp@intel.com/reproduce) If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot <lkp@intel.com> | Closes: https://lore.kernel.org/oe-kbuild-all/202307280004.UhGTxBbU-lkp@intel.com/ All warnings (new ones prefixed by >>): >> drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c:114:6: warning: no previous prototype for function 'dwmac1000_dma_init_channel' [-Wmissing-prototypes] void dwmac1000_dma_init_channel(struct stmmac_priv *priv, void __iomem *ioaddr, ^ drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c:114:1: note: declare 'static' if the function is not intended to be used outside of this translation unit void dwmac1000_dma_init_channel(struct stmmac_priv *priv, void __iomem *ioaddr, ^ static 1 warning generated. vim +/dwmac1000_dma_init_channel +114 drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c 113 > 114 void dwmac1000_dma_init_channel(struct stmmac_priv *priv, void __iomem *ioaddr, 115 struct stmmac_dma_cfg *dma_cfg, 116 u32 chan) 117 { 118 u32 value; 119 int txpbl = dma_cfg->txpbl ?: dma_cfg->pbl; 120 int rxpbl = dma_cfg->rxpbl ?: dma_cfg->pbl; 121 122 if (!priv->plat->dwmac_is_loongson) 123 return; 124 125 /* common channel control register config */ 126 value = readl(ioaddr + DMA_BUS_MODE + chan * DMA_CHAN_OFFSET); 127 128 /* 129 * Set the DMA PBL (Programmable Burst Length) mode. 130 * 131 * Note: before stmmac core 3.50 this mode bit was 4xPBL, and 132 * post 3.5 mode bit acts as 8*PBL. 133 */ 134 if (dma_cfg->pblx8) 135 value |= DMA_BUS_MODE_MAXPBL; 136 value |= DMA_BUS_MODE_USP; 137 value &= ~(DMA_BUS_MODE_PBL_MASK | DMA_BUS_MODE_RPBL_MASK); 138 value |= (txpbl << DMA_BUS_MODE_PBL_SHIFT); 139 value |= (rxpbl << DMA_BUS_MODE_RPBL_SHIFT); 140 141 /* Set the Fixed burst mode */ 142 if (dma_cfg->fixed_burst) 143 value |= DMA_BUS_MODE_FB; 144 145 /* Mixed Burst has no effect when fb is set */ 146 if (dma_cfg->mixed_burst) 147 value |= DMA_BUS_MODE_MB; 148 149 value |= DMA_BUS_MODE_ATDS; 150 151 if (dma_cfg->aal) 152 value |= DMA_BUS_MODE_AAL; 153 154 writel(value, ioaddr + DMA_BUS_MODE + chan * DMA_CHAN_OFFSET); 155 156 /* Mask interrupts by writing to CSR7 */ 157 writel(DMA_INTR_DEFAULT_MASK, 158 ioaddr + DMA_INTR_ENA + chan * DMA_CHAN_OFFSET); 159 } 160
On Thu, Jul 27, 2023 at 5:01 PM Andrew Lunn <andrew@lunn.ch> wrote: > > On Thu, Jul 27, 2023 at 03:15:46PM +0800, Feiyang Chen wrote: > > Some platforms have dwmac1000 implementations that support multi- > > channel. Extend the functions to add multi-channel support. > > > > + priv->plat->dwmac_is_loongson = false; > > I don't know this driver, so my comments could be wrong... > > Is this specific to loongson, or multi-channel? If you look at the > other bool in plat, they are all for features, not machines? Could > this actually be called priv->multi_chan_en ? > Hi, Andrew, It is specific to loongson. I think I can add some features instead of using dwmac_is_loongson. Thanks, Feiyang > Andrew
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c index 9015a61f804c..a9b42a122ed6 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c @@ -562,6 +562,7 @@ int dwmac1000_setup(struct stmmac_priv *priv) { dev_info(priv->device, "\tDWMAC1000\n"); + priv->plat->dwmac_is_loongson = false; priv->plat->dwmac_regs = &dwmac_default_dma_regs; return _dwmac1000_setup(priv); diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c index ce0e6ca6f3a2..efb219999a20 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c @@ -111,13 +111,61 @@ static void dwmac1000_dma_init(struct stmmac_priv *priv, void __iomem *ioaddr, writel(DMA_INTR_DEFAULT_MASK, ioaddr + DMA_INTR_ENA); } +void dwmac1000_dma_init_channel(struct stmmac_priv *priv, void __iomem *ioaddr, + struct stmmac_dma_cfg *dma_cfg, + u32 chan) +{ + u32 value; + int txpbl = dma_cfg->txpbl ?: dma_cfg->pbl; + int rxpbl = dma_cfg->rxpbl ?: dma_cfg->pbl; + + if (!priv->plat->dwmac_is_loongson) + return; + + /* common channel control register config */ + value = readl(ioaddr + DMA_BUS_MODE + chan * DMA_CHAN_OFFSET); + + /* + * Set the DMA PBL (Programmable Burst Length) mode. + * + * Note: before stmmac core 3.50 this mode bit was 4xPBL, and + * post 3.5 mode bit acts as 8*PBL. + */ + if (dma_cfg->pblx8) + value |= DMA_BUS_MODE_MAXPBL; + value |= DMA_BUS_MODE_USP; + value &= ~(DMA_BUS_MODE_PBL_MASK | DMA_BUS_MODE_RPBL_MASK); + value |= (txpbl << DMA_BUS_MODE_PBL_SHIFT); + value |= (rxpbl << DMA_BUS_MODE_RPBL_SHIFT); + + /* Set the Fixed burst mode */ + if (dma_cfg->fixed_burst) + value |= DMA_BUS_MODE_FB; + + /* Mixed Burst has no effect when fb is set */ + if (dma_cfg->mixed_burst) + value |= DMA_BUS_MODE_MB; + + value |= DMA_BUS_MODE_ATDS; + + if (dma_cfg->aal) + value |= DMA_BUS_MODE_AAL; + + writel(value, ioaddr + DMA_BUS_MODE + chan * DMA_CHAN_OFFSET); + + /* Mask interrupts by writing to CSR7 */ + writel(DMA_INTR_DEFAULT_MASK, + ioaddr + DMA_INTR_ENA + chan * DMA_CHAN_OFFSET); +} + static void dwmac1000_dma_init_rx(struct stmmac_priv *priv, void __iomem *ioaddr, struct stmmac_dma_cfg *dma_cfg, dma_addr_t dma_rx_phy, u32 chan) { /* RX descriptor base address list must be written into DMA CSR3 */ - writel(lower_32_bits(dma_rx_phy), ioaddr + DMA_RCV_BASE_ADDR); + writel(lower_32_bits(dma_rx_phy), ioaddr + DMA_RCV_BASE_ADDR + + chan * DMA_CHAN_OFFSET); } static void dwmac1000_dma_init_tx(struct stmmac_priv *priv, @@ -126,7 +174,8 @@ static void dwmac1000_dma_init_tx(struct stmmac_priv *priv, dma_addr_t dma_tx_phy, u32 chan) { /* TX descriptor base address list must be written into DMA CSR4 */ - writel(lower_32_bits(dma_tx_phy), ioaddr + DMA_TX_BASE_ADDR); + writel(lower_32_bits(dma_tx_phy), ioaddr + DMA_TX_BASE_ADDR + + chan * DMA_CHAN_OFFSET); } static u32 dwmac1000_configure_fc(u32 csr6, int rxfifosz) @@ -154,7 +203,7 @@ static void dwmac1000_dma_operation_mode_rx(struct stmmac_priv *priv, void __iomem *ioaddr, int mode, u32 channel, int fifosz, u8 qmode) { - u32 csr6 = readl(ioaddr + DMA_CONTROL); + u32 csr6 = readl(ioaddr + DMA_CONTROL + channel * DMA_CHAN_OFFSET); if (mode == SF_DMA_MODE) { pr_debug("GMAC: enable RX store and forward mode\n"); @@ -176,14 +225,14 @@ static void dwmac1000_dma_operation_mode_rx(struct stmmac_priv *priv, /* Configure flow control based on rx fifo size */ csr6 = dwmac1000_configure_fc(csr6, fifosz); - writel(csr6, ioaddr + DMA_CONTROL); + writel(csr6, ioaddr + DMA_CONTROL + channel * DMA_CHAN_OFFSET); } static void dwmac1000_dma_operation_mode_tx(struct stmmac_priv *priv, void __iomem *ioaddr, int mode, u32 channel, int fifosz, u8 qmode) { - u32 csr6 = readl(ioaddr + DMA_CONTROL); + u32 csr6 = readl(ioaddr + DMA_CONTROL + channel * DMA_CHAN_OFFSET); if (mode == SF_DMA_MODE) { pr_debug("GMAC: enable TX store and forward mode\n"); @@ -210,7 +259,7 @@ static void dwmac1000_dma_operation_mode_tx(struct stmmac_priv *priv, csr6 |= DMA_CONTROL_TTC_256; } - writel(csr6, ioaddr + DMA_CONTROL); + writel(csr6, ioaddr + DMA_CONTROL + channel * DMA_CHAN_OFFSET); } static void dwmac1000_dump_dma_regs(struct stmmac_priv *priv, @@ -273,12 +322,13 @@ static int dwmac1000_get_hw_feature(struct stmmac_priv *priv, static void dwmac1000_rx_watchdog(struct stmmac_priv *priv, void __iomem *ioaddr, u32 riwt, u32 queue) { - writel(riwt, ioaddr + DMA_RX_WATCHDOG); + writel(riwt, ioaddr + DMA_RX_WATCHDOG + queue * DMA_CHAN_OFFSET); } const struct stmmac_dma_ops dwmac1000_dma_ops = { .reset = dwmac_dma_reset, .init = dwmac1000_dma_init, + .init_chan = dwmac1000_dma_init_channel, .init_rx_chan = dwmac1000_dma_init_rx, .init_tx_chan = dwmac1000_dma_init_tx, .axi = dwmac1000_dma_axi, diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c b/drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c index 266f64148c1a..99838497b183 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac_lib.c @@ -71,63 +71,63 @@ int dwmac_dma_reset(void __iomem *ioaddr) void dwmac_enable_dma_transmission(struct stmmac_priv *priv, void __iomem *ioaddr, u32 chan) { - writel(1, ioaddr + DMA_XMT_POLL_DEMAND); + writel(1, ioaddr + DMA_XMT_POLL_DEMAND + chan * DMA_CHAN_OFFSET); } void dwmac_enable_dma_irq(struct stmmac_priv *priv, void __iomem *ioaddr, u32 chan, bool rx, bool tx) { - u32 value = readl(ioaddr + DMA_INTR_ENA); + u32 value = readl(ioaddr + DMA_INTR_ENA + chan * DMA_CHAN_OFFSET); if (rx) value |= DMA_INTR_DEFAULT_RX; if (tx) value |= DMA_INTR_DEFAULT_TX; - writel(value, ioaddr + DMA_INTR_ENA); + writel(value, ioaddr + DMA_INTR_ENA + chan * DMA_CHAN_OFFSET); } void dwmac_disable_dma_irq(struct stmmac_priv *priv, void __iomem *ioaddr, u32 chan, bool rx, bool tx) { - u32 value = readl(ioaddr + DMA_INTR_ENA); + u32 value = readl(ioaddr + DMA_INTR_ENA + chan * DMA_CHAN_OFFSET); if (rx) value &= ~DMA_INTR_DEFAULT_RX; if (tx) value &= ~DMA_INTR_DEFAULT_TX; - writel(value, ioaddr + DMA_INTR_ENA); + writel(value, ioaddr + DMA_INTR_ENA + chan * DMA_CHAN_OFFSET); } void dwmac_dma_start_tx(struct stmmac_priv *priv, void __iomem *ioaddr, u32 chan) { - u32 value = readl(ioaddr + DMA_CONTROL); + u32 value = readl(ioaddr + DMA_CONTROL + chan * DMA_CHAN_OFFSET); value |= DMA_CONTROL_ST; - writel(value, ioaddr + DMA_CONTROL); + writel(value, ioaddr + DMA_CONTROL + chan * DMA_CHAN_OFFSET); } void dwmac_dma_stop_tx(struct stmmac_priv *priv, void __iomem *ioaddr, u32 chan) { - u32 value = readl(ioaddr + DMA_CONTROL); + u32 value = readl(ioaddr + DMA_CONTROL + chan * DMA_CHAN_OFFSET); value &= ~DMA_CONTROL_ST; - writel(value, ioaddr + DMA_CONTROL); + writel(value, ioaddr + DMA_CONTROL + chan * DMA_CHAN_OFFSET); } void dwmac_dma_start_rx(struct stmmac_priv *priv, void __iomem *ioaddr, u32 chan) { - u32 value = readl(ioaddr + DMA_CONTROL); + u32 value = readl(ioaddr + DMA_CONTROL + chan * DMA_CHAN_OFFSET); value |= DMA_CONTROL_SR; - writel(value, ioaddr + DMA_CONTROL); + writel(value, ioaddr + DMA_CONTROL + chan * DMA_CHAN_OFFSET); } void dwmac_dma_stop_rx(struct stmmac_priv *priv, void __iomem *ioaddr, u32 chan) { - u32 value = readl(ioaddr + DMA_CONTROL); + u32 value = readl(ioaddr + DMA_CONTROL + chan * DMA_CHAN_OFFSET); value &= ~DMA_CONTROL_SR; - writel(value, ioaddr + DMA_CONTROL); + writel(value, ioaddr + DMA_CONTROL + chan * DMA_CHAN_OFFSET); } #ifdef DWMAC_DMA_DEBUG @@ -205,7 +205,7 @@ int dwmac_dma_interrupt(struct stmmac_priv *priv, void __iomem *ioaddr, { int ret = 0; /* read the status register (CSR5) */ - u32 intr_status = readl(ioaddr + DMA_STATUS); + u32 intr_status = readl(ioaddr + DMA_STATUS + chan * DMA_CHAN_OFFSET); #ifdef DWMAC_DMA_DEBUG /* Enable it to monitor DMA rx/tx status in case of critical problems */ diff --git a/include/linux/stmmac.h b/include/linux/stmmac.h index db61dc7c931d..5e68553433a7 100644 --- a/include/linux/stmmac.h +++ b/include/linux/stmmac.h @@ -342,5 +342,6 @@ struct plat_stmmacenet_data { const struct dwmac4_addrs *dwmac4_addrs; bool has_integrated_pcs; const struct dwmac_regs *dwmac_regs; + bool dwmac_is_loongson; }; #endif
Some platforms have dwmac1000 implementations that support multi- channel. Extend the functions to add multi-channel support. Signed-off-by: Feiyang Chen <chenfeiyang@loongson.cn> --- .../ethernet/stmicro/stmmac/dwmac1000_core.c | 1 + .../ethernet/stmicro/stmmac/dwmac1000_dma.c | 64 +++++++++++++++++-- .../net/ethernet/stmicro/stmmac/dwmac_lib.c | 28 ++++---- include/linux/stmmac.h | 1 + 4 files changed, 73 insertions(+), 21 deletions(-)