| Message ID | 20230717061831.1826878-8-victor.liu@nxp.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/bridge: imx: Add i.MX93 MIPI DSI support | expand |
On 17/07/2023 08:18, Liu Ying wrote: > According to Synopsys DW MIPI DSI host databook, HSTX and LPRX timeout > contention detections are measured in TO_CLK_DIVISION cycles. However, > the current driver programs magic values to TO_CLK_DIVISION, HSTX_TO_CNT > and LPRX_TO_CNT register fields, which makes timeout error event wrongly > happen for some video modes, at least for the typical 1920x1080p@60 video > mode read from a HDMI monitor driven by ADV7535 DSI to HDMI bridge. > While at it, the current driver doesn't enable interrupt to handle or > complain about the error status, so true error just happens silently > except for display distortions by visual check. > > Disable the timeout check by setting those timeout register fields to > zero for now until someone comes along with better computations for the > timeout values. Although the databook doesn't mention what happens when > they are set to zero, it turns out the false error doesn't happen for > the 1920x1080p@60 video mode at least. > > Signed-off-by: Liu Ying <victor.liu@nxp.com> > --- > drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c > index 536306ccea5a..0fcadf99e783 100644 > --- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c > +++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c > @@ -684,7 +684,7 @@ static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi) > * timeout clock division should be computed with the > * high speed transmission counter timeout and byte lane... > */ > - dsi_write(dsi, DSI_CLKMGR_CFG, TO_CLK_DIVISION(10) | > + dsi_write(dsi, DSI_CLKMGR_CFG, TO_CLK_DIVISION(0) | > TX_ESC_CLK_DIVISION(esc_clk_division)); > } > > @@ -747,7 +747,7 @@ static void dw_mipi_dsi_command_mode_config(struct dw_mipi_dsi *dsi) > * compute high speed transmission counter timeout according > * to the timeout clock division (TO_CLK_DIVISION) and byte lane... > */ > - dsi_write(dsi, DSI_TO_CNT_CFG, HSTX_TO_CNT(1000) | LPRX_TO_CNT(1000)); > + dsi_write(dsi, DSI_TO_CNT_CFG, HSTX_TO_CNT(0) | LPRX_TO_CNT(0)); > /* > * TODO dw drv improvements > * the Bus-Turn-Around Timeout Counter should be computed Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c index 536306ccea5a..0fcadf99e783 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c @@ -684,7 +684,7 @@ static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi) * timeout clock division should be computed with the * high speed transmission counter timeout and byte lane... */ - dsi_write(dsi, DSI_CLKMGR_CFG, TO_CLK_DIVISION(10) | + dsi_write(dsi, DSI_CLKMGR_CFG, TO_CLK_DIVISION(0) | TX_ESC_CLK_DIVISION(esc_clk_division)); } @@ -747,7 +747,7 @@ static void dw_mipi_dsi_command_mode_config(struct dw_mipi_dsi *dsi) * compute high speed transmission counter timeout according * to the timeout clock division (TO_CLK_DIVISION) and byte lane... */ - dsi_write(dsi, DSI_TO_CNT_CFG, HSTX_TO_CNT(1000) | LPRX_TO_CNT(1000)); + dsi_write(dsi, DSI_TO_CNT_CFG, HSTX_TO_CNT(0) | LPRX_TO_CNT(0)); /* * TODO dw drv improvements * the Bus-Turn-Around Timeout Counter should be computed
According to Synopsys DW MIPI DSI host databook, HSTX and LPRX timeout contention detections are measured in TO_CLK_DIVISION cycles. However, the current driver programs magic values to TO_CLK_DIVISION, HSTX_TO_CNT and LPRX_TO_CNT register fields, which makes timeout error event wrongly happen for some video modes, at least for the typical 1920x1080p@60 video mode read from a HDMI monitor driven by ADV7535 DSI to HDMI bridge. While at it, the current driver doesn't enable interrupt to handle or complain about the error status, so true error just happens silently except for display distortions by visual check. Disable the timeout check by setting those timeout register fields to zero for now until someone comes along with better computations for the timeout values. Although the databook doesn't mention what happens when they are set to zero, it turns out the false error doesn't happen for the 1920x1080p@60 video mode at least. Signed-off-by: Liu Ying <victor.liu@nxp.com> --- drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)