| Message ID | 20230801070019.219660-2-j-choudhary@ti.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Enable Display for J784S4 and AM69-SK platform | expand |
On 8/1/23 2:00 AM, Jayesh Choudhary wrote: > From: Siddharth Vadapalli <s-vadapalli@ti.com> > > The system controller node manages the CTRL_MMR0 region. > Add serdes_ln_ctrl node which is used for controlling the SERDES lane mux. > > Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> > [j-choudhary@ti.com: Fix serdes_ln_ctrl node] > Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com> > --- > arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 40 ++++++++++++++++++++++ > 1 file changed, 40 insertions(+) > > diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi > index 11f163e5cadf..8a816563706b 100644 > --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi > +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi > @@ -5,6 +5,10 @@ > * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ > */ > > +#include <dt-bindings/mux/mux.h> > + > +#include "k3-serdes.h" > + > &cbass_main { > msmc_ram: sram@70000000 { > compatible = "mmio-sram"; > @@ -26,6 +30,42 @@ l3cache-sram@200000 { > }; > }; > > + scm_conf: bus@100000 { > + compatible = "simple-bus"; > + reg = <0x00 0x00100000 0x00 0x1c000>; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x00 0x00 0x00100000 0x1c000>; > + > + serdes_ln_ctrl: mux-controller@4080 { > + compatible = "mmio-mux"; The parent is not a syscon node, this should be "reg-mux". https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/mux/reg-mux.yaml#n19 Andrew > + reg = <0x00004080 0x30>; > + #mux-control-cells = <1>; > + mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */ > + <0x4088 0x3>, <0x408c 0x3>, /* SERDES0 lane2/3 select */ > + <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */ > + <0x4098 0x3>, <0x409c 0x3>, /* SERDES1 lane2/3 select */ > + <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */ > + <0x40a8 0x3>, <0x40ac 0x3>; /* SERDES2 lane2/3 select */ > + idle-states = <J784S4_SERDES0_LANE0_PCIE1_LANE0>, > + <J784S4_SERDES0_LANE1_PCIE1_LANE1>, > + <J784S4_SERDES0_LANE2_IP3_UNUSED>, > + <J784S4_SERDES0_LANE3_USB>, > + <J784S4_SERDES1_LANE0_PCIE0_LANE0>, > + <J784S4_SERDES1_LANE1_PCIE0_LANE1>, > + <J784S4_SERDES1_LANE2_PCIE0_LANE2>, > + <J784S4_SERDES1_LANE3_PCIE0_LANE3>, > + <J784S4_SERDES2_LANE0_IP2_UNUSED>, > + <J784S4_SERDES2_LANE1_IP2_UNUSED>, > + <J784S4_SERDES2_LANE2_QSGMII_LANE1>, > + <J784S4_SERDES2_LANE3_QSGMII_LANE2>, > + <J784S4_SERDES4_LANE0_EDP_LANE0>, > + <J784S4_SERDES4_LANE1_EDP_LANE1>, > + <J784S4_SERDES4_LANE2_EDP_LANE2>, > + <J784S4_SERDES4_LANE3_EDP_LANE3>; > + }; > + }; > + > gic500: interrupt-controller@1800000 { > compatible = "arm,gic-v3"; > #address-cells = <2>;
diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi index 11f163e5cadf..8a816563706b 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi @@ -5,6 +5,10 @@ * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ */ +#include <dt-bindings/mux/mux.h> + +#include "k3-serdes.h" + &cbass_main { msmc_ram: sram@70000000 { compatible = "mmio-sram"; @@ -26,6 +30,42 @@ l3cache-sram@200000 { }; }; + scm_conf: bus@100000 { + compatible = "simple-bus"; + reg = <0x00 0x00100000 0x00 0x1c000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00 0x00 0x00100000 0x1c000>; + + serdes_ln_ctrl: mux-controller@4080 { + compatible = "mmio-mux"; + reg = <0x00004080 0x30>; + #mux-control-cells = <1>; + mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */ + <0x4088 0x3>, <0x408c 0x3>, /* SERDES0 lane2/3 select */ + <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */ + <0x4098 0x3>, <0x409c 0x3>, /* SERDES1 lane2/3 select */ + <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */ + <0x40a8 0x3>, <0x40ac 0x3>; /* SERDES2 lane2/3 select */ + idle-states = <J784S4_SERDES0_LANE0_PCIE1_LANE0>, + <J784S4_SERDES0_LANE1_PCIE1_LANE1>, + <J784S4_SERDES0_LANE2_IP3_UNUSED>, + <J784S4_SERDES0_LANE3_USB>, + <J784S4_SERDES1_LANE0_PCIE0_LANE0>, + <J784S4_SERDES1_LANE1_PCIE0_LANE1>, + <J784S4_SERDES1_LANE2_PCIE0_LANE2>, + <J784S4_SERDES1_LANE3_PCIE0_LANE3>, + <J784S4_SERDES2_LANE0_IP2_UNUSED>, + <J784S4_SERDES2_LANE1_IP2_UNUSED>, + <J784S4_SERDES2_LANE2_QSGMII_LANE1>, + <J784S4_SERDES2_LANE3_QSGMII_LANE2>, + <J784S4_SERDES4_LANE0_EDP_LANE0>, + <J784S4_SERDES4_LANE1_EDP_LANE1>, + <J784S4_SERDES4_LANE2_EDP_LANE2>, + <J784S4_SERDES4_LANE3_EDP_LANE3>; + }; + }; + gic500: interrupt-controller@1800000 { compatible = "arm,gic-v3"; #address-cells = <2>;