[V4,4/7] clk: qcom: gcc-qdu1000: Update GCC clocks as per the latest hw version

Commit Message

Imran Shaik July 19, 2023, 4:14 a.m. UTC

Update the GCC clocks as per the latest hw version of QDU1000 and
QRU100 SoCs.

Co-developed-by: Taniya Das <[e-mail]>
Signed-off-by: Taniya Das <[e-mail]>
Signed-off-by: Imran Shaik <[e-mail]>
---
Changes since v3:
 - None
Changes since v2:
 - Split the patch as per the review comments
 - Newly added

 drivers/clk/qcom/gcc-qdu1000.c | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

Comments

Konrad Dybcio July 26, 2023, 3:42 p.m. UTC | #1

On 19.07.2023 06:14, Imran Shaik wrote:
> Update the GCC clocks as per the latest hw version of QDU1000 and
> QRU100 SoCs.
> 
> Co-developed-by: Taniya Das <[e-mail]>
> Signed-off-by: Taniya Das <[e-mail]>
> Signed-off-by: Imran Shaik <[e-mail]>
> ---
[...]

> +	[GCC_GPLL1_OUT_EVEN] = &gcc_gpll1_out_even.clkr,
So, this clock was there before, but it was never registered with the
clock framework, even though it was referenced as a parent..

Sounds like a bug!

Konrad

Imran Shaik Aug. 2, 2023, 8:10 a.m. UTC | #2

On 7/26/2023 9:12 PM, Konrad Dybcio wrote:
> On 19.07.2023 06:14, Imran Shaik wrote:
>> Update the GCC clocks as per the latest hw version of QDU1000 and
>> QRU100 SoCs.
>>
>> Co-developed-by: Taniya Das <[e-mail]>
>> Signed-off-by: Taniya Das <[e-mail]>
>> Signed-off-by: Imran Shaik <[e-mail]>
>> ---
> [...]
> 
>> +	[GCC_GPLL1_OUT_EVEN] = &gcc_gpll1_out_even.clkr,
> So, this clock was there before, but it was never registered with the
> clock framework, even though it was referenced as a parent..
> 
> Sounds like a bug!
> > Konrad

Yes, I will split this change adding the fixes tag and push another series.

Thanks,
Imran

Patch

diff --git a/drivers/clk/qcom/gcc-qdu1000.c b/drivers/clk/qcom/gcc-qdu1000.c
index 8df7b7983968..991fb2bc97e9 100644
--- a/drivers/clk/qcom/gcc-qdu1000.c
+++ b/drivers/clk/qcom/gcc-qdu1000.c
@@ -1131,6 +1131,26 @@  static struct clk_branch gcc_ddrss_ecpri_dma_clk = {
 	},
 };
 
+static struct clk_branch gcc_ddrss_ecpri_gsi_clk = {
+	.halt_reg = 0x54298,
+	.halt_check = BRANCH_HALT_VOTED,
+	.hwcg_reg = 0x54298,
+	.hwcg_bit = 1,
+	.clkr = {
+		.enable_reg = 0x54298,
+		.enable_mask = BIT(0),
+		.hw.init = &(const struct clk_init_data) {
+			.name = "gcc_ddrss_ecpri_gsi_clk",
+			.parent_hws = (const struct clk_hw*[]) {
+				&gcc_aggre_noc_ecpri_gsi_clk_src.clkr.hw,
+			},
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_aon_ops,
+		},
+	},
+};
+
 static struct clk_branch gcc_ecpri_ahb_clk = {
 	.halt_reg = 0x3a008,
 	.halt_check = BRANCH_HALT_VOTED,
@@ -2521,6 +2541,8 @@  static struct clk_regmap *gcc_qdu1000_clocks[] = {
 	[GCC_AGGRE_NOC_ECPRI_GSI_CLK] = &gcc_aggre_noc_ecpri_gsi_clk.clkr,
 	[GCC_PCIE_0_PHY_AUX_CLK_SRC] = &gcc_pcie_0_phy_aux_clk_src.clkr,
 	[GCC_PCIE_0_PIPE_CLK_SRC] = &gcc_pcie_0_pipe_clk_src.clkr,
+	[GCC_GPLL1_OUT_EVEN] = &gcc_gpll1_out_even.clkr,
+	[GCC_DDRSS_ECPRI_GSI_CLK] = &gcc_ddrss_ecpri_gsi_clk.clkr,
 };
 
 static const struct qcom_reset_map gcc_qdu1000_resets[] = {