| Message ID | 20230725183939.2741025-5-fan.ni@samsung.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [Qemu,v2,1/9] hw/cxl/cxl-mailbox-utils: Add dc_event_log_size field to output payload of identify memory device command | expand |
On Tue, 25 Jul 2023 18:39:55 +0000 Fan Ni <fan.ni@samsung.com> wrote: > From: Fan Ni <nifan@outlook.com> > > With the change, when setting up memory for type3 memory device, we can > create DC regions > A property 'num-dc-regions' is added to ct3_props to allow users to pass the > number of DC regions to create. To make it easier, other region parameters > like region base, length, and block size are hard coded. If needed, > these parameters can be added easily. Longer term I think we need to have an interface based on one or more memory backends. Gets fiddly if we allow live configuration of the regions but for static regions it should be easy and look like the vmem and pmem already in place. This is good for testing in the meantime. > > With the change, we can create DC regions with proper kernel side > support as below: > > region=$(cat /sys/bus/cxl/devices/decoder0.0/create_dc_region) > echo $region> /sys/bus/cxl/devices/decoder0.0/create_dc_region > echo 256 > /sys/bus/cxl/devices/$region/interleave_granularity > echo 1 > /sys/bus/cxl/devices/$region/interleave_ways > > echo "dc0" >/sys/bus/cxl/devices/decoder2.0/mode > echo 0x40000000 >/sys/bus/cxl/devices/decoder2.0/dpa_size > > echo 0x40000000 > /sys/bus/cxl/devices/$region/size > echo "decoder2.0" > /sys/bus/cxl/devices/$region/target0 > echo 1 > /sys/bus/cxl/devices/$region/commit > echo $region > /sys/bus/cxl/drivers/cxl_region/bind > > Signed-off-by: Fan Ni <fan.ni@samsung.com> > --- > hw/mem/cxl_type3.c | 33 +++++++++++++++++++++++++++++++++ > 1 file changed, 33 insertions(+) > > diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c > index 3d7acffcb7..b29bb2309a 100644 > --- a/hw/mem/cxl_type3.c > +++ b/hw/mem/cxl_type3.c > @@ -707,6 +707,34 @@ static void ct3d_reg_write(void *opaque, hwaddr offset, uint64_t value, > } > } > > +/* > + * Create a dc region to test "Get Dynamic Capacity Configuration" command. > + */ > +static int cxl_create_dc_regions(CXLType3Dev *ct3d) > +{ > + int i; > + uint64_t region_base = (ct3d->hostvmem ? ct3d->hostvmem->size : 0) > + + (ct3d->hostpmem ? ct3d->hostpmem->size : 0); This is getting hard to read. Perhaps long hand version with if statements is easier? uint64_t region_base = 0; if (ct3d->hostvmem) { region_base += ct3d->hostvmem->size; } etc. > + uint64_t region_len = (uint64_t)2 * 1024 * 1024 * 1024; include/qemu/units.h GiB and MiB as appropraite. > + uint64_t decode_len = 4; /* 4*256MB */ > + uint64_t blk_size = 2 * 1024 * 1024; > + struct CXLDCD_Region *region; > + > + for (i = 0; i < ct3d->dc.num_regions; i++) { > + region = &ct3d->dc.regions[i]; > + region->base = region_base; > + region->decode_len = decode_len; > + region->len = region_len; > + region->block_size = blk_size; > + /* dsmad_handle is set when creating cdat table entries */ > + region->flags = 0; > + > + region_base += region->len; > + } > + > + return 0; > +} > + > static bool cxl_setup_memory(CXLType3Dev *ct3d, Error **errp) > { > DeviceState *ds = DEVICE(ct3d); > @@ -775,6 +803,10 @@ static bool cxl_setup_memory(CXLType3Dev *ct3d, Error **errp) > g_free(p_name); > } > > + if (cxl_create_dc_regions(ct3d)) { > + return false; > + } > + > return true; > } > > @@ -1068,6 +1100,7 @@ static Property ct3_props[] = { > DEFINE_PROP_UINT64("sn", CXLType3Dev, sn, UI64_NULL), > DEFINE_PROP_STRING("cdat", CXLType3Dev, cxl_cstate.cdat.filename), > DEFINE_PROP_UINT16("spdm", CXLType3Dev, spdm_port, 0), > + DEFINE_PROP_UINT8("num-dc-regions", CXLType3Dev, dc.num_regions, 0), > DEFINE_PROP_END_OF_LIST(), > }; >
diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c index 3d7acffcb7..b29bb2309a 100644 --- a/hw/mem/cxl_type3.c +++ b/hw/mem/cxl_type3.c @@ -707,6 +707,34 @@ static void ct3d_reg_write(void *opaque, hwaddr offset, uint64_t value, } } +/* + * Create a dc region to test "Get Dynamic Capacity Configuration" command. + */ +static int cxl_create_dc_regions(CXLType3Dev *ct3d) +{ + int i; + uint64_t region_base = (ct3d->hostvmem ? ct3d->hostvmem->size : 0) + + (ct3d->hostpmem ? ct3d->hostpmem->size : 0); + uint64_t region_len = (uint64_t)2 * 1024 * 1024 * 1024; + uint64_t decode_len = 4; /* 4*256MB */ + uint64_t blk_size = 2 * 1024 * 1024; + struct CXLDCD_Region *region; + + for (i = 0; i < ct3d->dc.num_regions; i++) { + region = &ct3d->dc.regions[i]; + region->base = region_base; + region->decode_len = decode_len; + region->len = region_len; + region->block_size = blk_size; + /* dsmad_handle is set when creating cdat table entries */ + region->flags = 0; + + region_base += region->len; + } + + return 0; +} + static bool cxl_setup_memory(CXLType3Dev *ct3d, Error **errp) { DeviceState *ds = DEVICE(ct3d); @@ -775,6 +803,10 @@ static bool cxl_setup_memory(CXLType3Dev *ct3d, Error **errp) g_free(p_name); } + if (cxl_create_dc_regions(ct3d)) { + return false; + } + return true; } @@ -1068,6 +1100,7 @@ static Property ct3_props[] = { DEFINE_PROP_UINT64("sn", CXLType3Dev, sn, UI64_NULL), DEFINE_PROP_STRING("cdat", CXLType3Dev, cxl_cstate.cdat.filename), DEFINE_PROP_UINT16("spdm", CXLType3Dev, spdm_port, 0), + DEFINE_PROP_UINT8("num-dc-regions", CXLType3Dev, dc.num_regions, 0), DEFINE_PROP_END_OF_LIST(), };