diff mbox series

[v3,1/6] target/loongarch: Add loongarch32 mode for loongarch64-softmmu

Message ID 20230807094505.2030603-2-c@jia.je (mailing list archive)
State New, archived
Headers show
Series Add loongarch32 mode for loongarch64-softmmu | expand

Commit Message

Jiajie Chen Aug. 7, 2023, 9:45 a.m. UTC 
This commit adds loongarch32 mode to loongarch64-softmmu.

Signed-off-by: Jiajie Chen <c@jia.je>
---
 target/loongarch/cpu.h | 7 +++++++
 1 file changed, 7 insertions(+)

Comments

Richard Henderson Aug. 7, 2023, 3:13 p.m. UTC | #1 
On 8/7/23 02:45, Jiajie Chen wrote:
> This commit adds loongarch32 mode to loongarch64-softmmu.
> 
> Signed-off-by: Jiajie Chen <c@jia.je>
> ---
>   target/loongarch/cpu.h | 7 +++++++
>   1 file changed, 7 insertions(+)
> 
> diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
> index fa371ca8ba..43c73e6363 100644
> --- a/target/loongarch/cpu.h
> +++ b/target/loongarch/cpu.h
> @@ -272,9 +272,16 @@ struct LoongArchTLB {
>   };
>   typedef struct LoongArchTLB LoongArchTLB;
>   
> +/* Current LoongArch mode */
> +typedef enum LoongArchMode {
> +    LA32 = 0,
> +    LA64 = 1,
> +} LoongArchMode;
> +
>   typedef struct CPUArchState {
>       uint64_t gpr[32];
>       uint64_t pc;
> +    LoongArchMode mode;

This is not how the hardware works.
This data is stored in CPUCFG.1.ARCH.


r~
Jiajie Chen Aug. 7, 2023, 3:14 p.m. UTC | #2 
On 2023/8/7 23:13, Richard Henderson wrote:
> On 8/7/23 02:45, Jiajie Chen wrote:
>> This commit adds loongarch32 mode to loongarch64-softmmu.
>>
>> Signed-off-by: Jiajie Chen <c@jia.je>
>> ---
>>   target/loongarch/cpu.h | 7 +++++++
>>   1 file changed, 7 insertions(+)
>>
>> diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
>> index fa371ca8ba..43c73e6363 100644
>> --- a/target/loongarch/cpu.h
>> +++ b/target/loongarch/cpu.h
>> @@ -272,9 +272,16 @@ struct LoongArchTLB {
>>   };
>>   typedef struct LoongArchTLB LoongArchTLB;
>>   +/* Current LoongArch mode */
>> +typedef enum LoongArchMode {
>> +    LA32 = 0,
>> +    LA64 = 1,
>> +} LoongArchMode;
>> +
>>   typedef struct CPUArchState {
>>       uint64_t gpr[32];
>>       uint64_t pc;
>> +    LoongArchMode mode;
>
> This is not how the hardware works.
> This data is stored in CPUCFG.1.ARCH.
Okay, I will change to use CFGCFG.1.ARCH instead in v4.
>
>
> r~
diff mbox series

Patch

diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
index fa371ca8ba..43c73e6363 100644
--- a/target/loongarch/cpu.h
+++ b/target/loongarch/cpu.h
@@ -272,9 +272,16 @@  struct LoongArchTLB {
 };
 typedef struct LoongArchTLB LoongArchTLB;
 
+/* Current LoongArch mode */
+typedef enum LoongArchMode {
+    LA32 = 0,
+    LA64 = 1,
+} LoongArchMode;
+
 typedef struct CPUArchState {
     uint64_t gpr[32];
     uint64_t pc;
+    LoongArchMode mode;
 
     fpr_t fpr[32];
     float_status fp_status;