| Message ID | 20230807153307.22174-3-a-bhatia1@ti.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | arm64: ti: k3-am62: Add display support | expand |
Hello Aradhya, On 07/08/23 21:03, Aradhya Bhatia wrote: > Add Display SubSystem (DSS) DT node for the AM625 SoC. > > The DSS supports one each of video pipeline (vid) and video-lite > pipeline (vidl1). It outputs OLDI signals on one video port (VP1) and > DPI signals on another (VP2). The video ports are connected to the > pipelines via 2 identical overlay managers (ovr1 and ovr2). > > Signed-off-by: Aradhya Bhatia <a-bhatia1@ti.com> > --- > arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 25 ++++++++++++++++++++++++ > 1 file changed, 25 insertions(+) > > diff --git a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi > index ef90b2bc81eb..6cdca8df1091 100644 > --- a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi > +++ b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi > @@ -717,6 +717,31 @@ cpts@3d000 { > }; > }; > > + dss: dss@30200000 { > + compatible = "ti,am625-dss"; > + reg = <0x00 0x30200000 0x00 0x1000>, /* common */ > + <0x00 0x30202000 0x00 0x1000>, /* vidl1 */ > + <0x00 0x30206000 0x00 0x1000>, /* vid */ > + <0x00 0x30207000 0x00 0x1000>, /* ovr1 */ > + <0x00 0x30208000 0x00 0x1000>, /* ovr2 */ > + <0x00 0x3020a000 0x00 0x1000>, /* vp1: Used for OLDI */ > + <0x00 0x3020b000 0x00 0x1000>; /* vp2: Used as DPI Out */ > + reg-names = "common", "vidl1", "vid", > + "ovr1", "ovr2", "vp1", "vp2"; Indentation is off here. > + power-domains = <&k3_pds 186 TI_SCI_PD_EXCLUSIVE>; > + clocks = <&k3_clks 186 6>, > + <&k3_clks 186 0>, > + <&k3_clks 186 2>; > + clock-names = "fck", "vp1", "vp2"; > + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; > + status = "disabled"; > + > + dss_ports: ports { > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + }; > + > hwspinlock: spinlock@2a000000 { > compatible = "ti,am64-hwspinlock"; > reg = <0x00 0x2a000000 0x00 0x1000>;
diff --git a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi index ef90b2bc81eb..6cdca8df1091 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi @@ -717,6 +717,31 @@ cpts@3d000 { }; }; + dss: dss@30200000 { + compatible = "ti,am625-dss"; + reg = <0x00 0x30200000 0x00 0x1000>, /* common */ + <0x00 0x30202000 0x00 0x1000>, /* vidl1 */ + <0x00 0x30206000 0x00 0x1000>, /* vid */ + <0x00 0x30207000 0x00 0x1000>, /* ovr1 */ + <0x00 0x30208000 0x00 0x1000>, /* ovr2 */ + <0x00 0x3020a000 0x00 0x1000>, /* vp1: Used for OLDI */ + <0x00 0x3020b000 0x00 0x1000>; /* vp2: Used as DPI Out */ + reg-names = "common", "vidl1", "vid", + "ovr1", "ovr2", "vp1", "vp2"; + power-domains = <&k3_pds 186 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 186 6>, + <&k3_clks 186 0>, + <&k3_clks 186 2>; + clock-names = "fck", "vp1", "vp2"; + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + + dss_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + hwspinlock: spinlock@2a000000 { compatible = "ti,am64-hwspinlock"; reg = <0x00 0x2a000000 0x00 0x1000>;
Add Display SubSystem (DSS) DT node for the AM625 SoC. The DSS supports one each of video pipeline (vid) and video-lite pipeline (vidl1). It outputs OLDI signals on one video port (VP1) and DPI signals on another (VP2). The video ports are connected to the pipelines via 2 identical overlay managers (ovr1 and ovr2). Signed-off-by: Aradhya Bhatia <a-bhatia1@ti.com> --- arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 25 ++++++++++++++++++++++++ 1 file changed, 25 insertions(+)