| Message ID | 20230808015506.1705140-8-c@jia.je (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add la32 & va32 mode for loongarch64-softmmu | expand |
On 8/7/23 18:54, Jiajie Chen wrote: > --- a/target/loongarch/translate.c > +++ b/target/loongarch/translate.c > @@ -119,6 +119,9 @@ static void loongarch_tr_init_disas_context(DisasContextBase *dcbase, > ctx->vl = LSX_LEN; > } > > + ctx->la32 = LOONGARCH_CPUCFG_ARCH(env, LA32); > + ctx->va32 = (ctx->base.tb->flags & HW_FLAGS_VA32) != 0; > + > ctx->zero = tcg_constant_tl(0); > } > > diff --git a/target/loongarch/translate.h b/target/loongarch/translate.h > index 7f60090580..828f1185d2 100644 > --- a/target/loongarch/translate.h > +++ b/target/loongarch/translate.h > @@ -33,6 +33,8 @@ typedef struct DisasContext { > uint16_t plv; > int vl; /* Vector length */ > TCGv zero; > + bool la32; /* LoongArch32 mode */ Because if the LA32 Restricted (or simplified), let's make this la64. Otherwise, Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~
diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h index 396869c3b6..69589f0aef 100644 --- a/target/loongarch/cpu.h +++ b/target/loongarch/cpu.h @@ -445,15 +445,24 @@ static inline int cpu_mmu_index(CPULoongArchState *env, bool ifetch) #define HW_FLAGS_CRMD_PG R_CSR_CRMD_PG_MASK /* 0x10 */ #define HW_FLAGS_EUEN_FPE 0x04 #define HW_FLAGS_EUEN_SXE 0x08 +#define HW_FLAGS_VA32 0x20 static inline void cpu_get_tb_cpu_state(CPULoongArchState *env, vaddr *pc, uint64_t *cs_base, uint32_t *flags) { + /* VA32 if LA32 or VA32L[1-3] */ + uint32_t va32 = LOONGARCH_CPUCFG_ARCH(env, LA32); + uint64_t plv = FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PLV); + if (plv >= 1 && (FIELD_EX64(env->CSR_MISC, CSR_MISC, VA32) & (1 << plv))) { + va32 = 1; + } + *pc = env->pc; *cs_base = 0; *flags = env->CSR_CRMD & (R_CSR_CRMD_PLV_MASK | R_CSR_CRMD_PG_MASK); *flags |= FIELD_EX64(env->CSR_EUEN, CSR_EUEN, FPE) * HW_FLAGS_EUEN_FPE; *flags |= FIELD_EX64(env->CSR_EUEN, CSR_EUEN, SXE) * HW_FLAGS_EUEN_SXE; + *flags |= va32 * HW_FLAGS_VA32; } void loongarch_cpu_list(void); diff --git a/target/loongarch/translate.c b/target/loongarch/translate.c index 3146a2d4ac..f1e5fe4cf8 100644 --- a/target/loongarch/translate.c +++ b/target/loongarch/translate.c @@ -119,6 +119,9 @@ static void loongarch_tr_init_disas_context(DisasContextBase *dcbase, ctx->vl = LSX_LEN; } + ctx->la32 = LOONGARCH_CPUCFG_ARCH(env, LA32); + ctx->va32 = (ctx->base.tb->flags & HW_FLAGS_VA32) != 0; + ctx->zero = tcg_constant_tl(0); } diff --git a/target/loongarch/translate.h b/target/loongarch/translate.h index 7f60090580..828f1185d2 100644 --- a/target/loongarch/translate.h +++ b/target/loongarch/translate.h @@ -33,6 +33,8 @@ typedef struct DisasContext { uint16_t plv; int vl; /* Vector length */ TCGv zero; + bool la32; /* LoongArch32 mode */ + bool va32; /* 32-bit virtual address */ } DisasContext; void generate_exception(DisasContext *ctx, int excp);
Add LA32 and VA32(32-bit Virtual Address) to DisasContext to allow the translator to reject doubleword instructions in LA32 mode for example. Signed-off-by: Jiajie Chen <c@jia.je> --- target/loongarch/cpu.h | 9 +++++++++ target/loongarch/translate.c | 3 +++ target/loongarch/translate.h | 2 ++ 3 files changed, 14 insertions(+)